Searched refs:cfgPSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL (Results 1 - 2 of 2) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/nbio/
H A Dnbio_6_1_offset.h121 #define cfgPSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e macro
H A Dnbio_7_4_offset.h121 #define cfgPSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e macro

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