Searched refs:cfgPSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL (Results 1 - 2 of 2) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/nbio/
H A Dnbio_2_3_offset.h10362 #define cfgPSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL 0xfffe0000046c macro
[all...]
H A Dnbio_4_3_0_offset.h15159 #define cfgPSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL macro
[all...]

Completed in 485 milliseconds