Searched refs:cfgPSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL (Results 1 - 2 of 2) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/nbio/
H A Dnbio_2_3_offset.h10358 #define cfgPSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL 0xfffe00000464 macro
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H A Dnbio_4_3_0_offset.h15155 #define cfgPSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL macro
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