Searched refs:cfgPSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL (Results 1 - 2 of 2) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/nbio/
H A Dnbio_2_3_offset.h807 #define cfgPSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 macro
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H A Dnbio_4_3_0_offset.h2653 #define cfgPSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL 0xfffe00000288 macro
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