Searched refs:cfgBIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_CNTL (Results 1 - 2 of 2) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_4_offset.h1108 #define cfgBIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_CNTL 0x0474 macro
H A Dnbio_2_3_offset.h2221 #define cfgBIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_CNTL 0x0474 macro
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