/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn321/ |
H A D | dcn321_fpu.h | 32 void dcn321_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);
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H A D | dcn321_fpu.c | 344 static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk_bw_params *bw_params, argument 365 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_clk_data.dcfclk_mhz) 366 max_clk_data.dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; 367 if (bw_params->clk_table.entries[i].fclk_mhz > max_clk_data.fclk_mhz) 368 max_clk_data.fclk_mhz = bw_params->clk_table.entries[i].fclk_mhz; 369 if (bw_params->clk_table.entries[i].memclk_mhz > max_clk_data.memclk_mhz) 370 max_clk_data.memclk_mhz = bw_params->clk_table.entries[i].memclk_mhz; 371 if (bw_params->clk_table.entries[i].dispclk_mhz > max_clk_data.dispclk_mhz) 372 max_clk_data.dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; 373 if (bw_params 610 dcn321_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) argument [all...] |
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn302/ |
H A D | dcn302_fpu.h | 30 void dcn302_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
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H A D | dcn302_fpu.c | 195 void dcn302_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) argument 220 if (bw_params->clk_table.entries[0].memclk_mhz) { 224 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) 225 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; 226 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) 227 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; 228 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) 229 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; 230 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) 231 max_phyclk_mhz = bw_params [all...] |
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn303/ |
H A D | dcn303_fpu.h | 29 void dcn303_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
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H A D | dcn303_fpu.c | 191 void dcn303_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) argument 216 if (bw_params->clk_table.entries[0].memclk_mhz) { 220 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) 221 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; 222 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) 223 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; 224 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) 225 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; 226 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) 227 max_phyclk_mhz = bw_params [all...] |
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn302/ |
H A D | dcn302_resource.h | 36 void dcn302_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn303/ |
H A D | dcn303_resource.h | 18 void dcn303_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn314/ |
H A D | dcn314_fpu.h | 35 void dcn314_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn31/ |
H A D | dcn31_fpu.h | 46 void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params); 47 void dcn315_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params); 48 void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/ |
H A D | dcn314_clk_mgr.c | 436 static void dcn314_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn314_watermarks *table) argument 444 if (!bw_params->wm_table.entries[i].valid) 447 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; 448 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; 459 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; 462 bw_params->clk_table.entries[i].dcfclk_mhz; 505 dcn314_build_watermark_ranges(clk_mgr_base->bw_params, table); 571 struct clk_bw_params *bw_params = clk_mgr->base.bw_params; local 572 struct clk_limit_table_entry def_max = bw_params [all...] |
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/ |
H A D | dcn315_clk_mgr.c | 381 static void dcn315_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn315_watermarks *table) argument 389 if (!bw_params->wm_table.entries[i].valid) 392 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; 393 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; 404 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; 407 bw_params->clk_table.entries[i].dcfclk_mhz; 450 dcn315_build_watermark_ranges(clk_mgr_base->bw_params, table); 485 struct clk_bw_params *bw_params = clk_mgr->base.bw_params; local 487 struct clk_limit_table_entry def_max = bw_params [all...] |
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn301/ |
H A D | dcn301_fpu.h | 29 void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
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H A D | dcn301_fpu.c | 323 void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) argument 327 struct clk_limit_table *clk_table = &bw_params->clk_table; 338 dcn3_01_soc.num_chans = bw_params->num_channels; 421 struct clk_bw_params *bw_params = dc->clk_mgr->bw_params; local 423 ASSERT(bw_params); 426 vlevel_max = bw_params->clk_table.num_entries - 1; 429 table_entry = &bw_params->wm_table.entries[WM_D]; 437 table_entry = &bw_params->wm_table.entries[WM_C]; 442 table_entry = &bw_params [all...] |
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn30/ |
H A D | dcn30_fpu.c | 370 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) { 373 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; 374 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us; 375 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us; 413 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; 432 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) { 437 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us; 438 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us; 439 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us; 459 if (dc->clk_mgr->bw_params 639 dcn30_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params, struct dc_bounding_box_max_clk *dcn30_bb_max_clk, unsigned int *dcfclk_mhz, unsigned int *dram_speed_mts) argument [all...] |
H A D | dcn30_fpu.h | 61 struct clk_bw_params *bw_params,
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/ |
H A D | dcn30_clk_mgr.c | 97 entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]); 118 if (!clk_mgr_base->bw_params) 133 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz, 139 &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz, 144 &clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz, 150 &clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz, 155 &clk_mgr_base->bw_params->clk_table.entries[0].dppclk_mhz, 160 &clk_mgr_base->bw_params->clk_table.entries[0].phyclk_mhz, 253 if ((new_clocks->dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) != 254 (clk_mgr_base->clks.dramclk_khz <= dc->clk_mgr->bw_params [all...] |
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/ |
H A D | dcn316_clk_mgr.c | 343 static void dcn316_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn316_watermarks *table) argument 351 if (!bw_params->wm_table.entries[i].valid) 354 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; 355 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; 366 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; 369 bw_params->clk_table.entries[i].dcfclk_mhz; 412 dcn316_build_watermark_ranges(clk_mgr_base->bw_params, table); 483 struct clk_bw_params *bw_params = clk_mgr->base.bw_params; local 505 bw_params [all...] |
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/ |
H A D | dcn32_clk_mgr.c | 144 entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]); 159 struct clk_limit_num_entries *num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk; 169 if (!clk_mgr_base->bw_params) 183 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz, 185 clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DCFCLK); 189 &clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz, 191 clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_SOCCLK); 196 &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz, 198 clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz = 204 &clk_mgr_base->bw_params [all...] |
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn32/ |
H A D | dcn32_fpu.c | 181 uint16_t min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz; 182 uint16_t min_dcfclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz; 190 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = dcfclk_mhz_for_the_second_state; 192 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz; 194 if (clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz) 195 setb_min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz; 198 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true; 199 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us; 200 clk_mgr->base.bw_params 2316 dcn32_patch_dpm_table(struct clk_bw_params *bw_params) argument 2448 build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk_bw_params *bw_params, struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries) argument 2697 dcn32_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) argument [all...] |
H A D | dcn32_fpu.h | 62 void dcn32_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params); 70 void dcn32_patch_dpm_table(struct clk_bw_params *bw_params);
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn20/ |
H A D | dcn20_fpu.h | 83 void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params); 85 void dcn21_clk_mgr_set_bw_params_wm_table(struct clk_bw_params *bw_params);
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/ |
H A D | dcn31_clk_mgr.c | 421 static void dcn31_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn31_watermarks *table) argument 429 if (!bw_params->wm_table.entries[i].valid) 432 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; 433 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; 444 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; 447 bw_params->clk_table.entries[i].dcfclk_mhz; 490 dcn31_build_watermark_ranges(clk_mgr_base->bw_params, table); 560 struct clk_bw_params *bw_params = clk_mgr->base.bw_params; local 582 bw_params [all...] |
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/ |
H A D | vg_clk_mgr.c | 386 static void vg_build_watermark_ranges(struct clk_bw_params *bw_params, struct watermarks *table) argument 394 if (!bw_params->wm_table.entries[i].valid) 397 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; 398 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; 409 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; 412 bw_params->clk_table.entries[i].dcfclk_mhz; 456 vg_build_watermark_ranges(clk_mgr_base->bw_params, table); 563 struct clk_bw_params *bw_params = clk_mgr->base.bw_params; local 584 bw_params [all...] |
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/ |
H A D | rn_clk_mgr.c | 454 static void build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_range_sets *ranges) argument 462 if (!bw_params->wm_table.entries[i].valid) 465 ranges->reader_wm_sets[num_valid_sets].wm_inst = bw_params->wm_table.entries[i].wm_inst; 466 ranges->reader_wm_sets[num_valid_sets].wm_type = bw_params->wm_table.entries[i].wm_type; 477 ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; 479 ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; 518 build_watermark_ranges(clk_mgr_base->bw_params, &clk_mgr_base->ranges); 639 static void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct dpm_clocks *clock_table, struct integrated_info *bios_info) argument 662 bw_params->clk_table.num_entries = j + 1; 664 for (i = 0; i < bw_params [all...] |