Searched refs:WatermarkRow (Results 1 - 25 of 38) sorted by relevance

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/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_smu13_driver_if.h42 WatermarkRowGeneric_t WatermarkRow[NUM_WM_RANGES]; member in struct:__anon275
H A Dsmu13_driver_if.h75 WatermarkRowGeneric_t WatermarkRow[NUM_WM_RANGES]; member in struct:__anon281
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/
H A Ddcn316_clk_mgr.c354 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
355 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
357 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
358 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
360 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
362 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
365 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
368 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
373 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
374 table->WatermarkRow[WM_DCFCL
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H A Ddcn316_smu.h98 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member in struct:dcn316_watermarks
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddcn30_smu11_driver_if.h53 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member in struct:__anon244
H A Ddcn30_clk_mgr.c341 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MinClock = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.min_dcfclk;
342 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MaxClock = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.max_dcfclk;
343 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MinUclk = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.min_uclk;
344 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MaxUclk = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.max_uclk;
345 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].WmSetting = i;
346 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.wm_type;
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_clk_mgr.c432 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
433 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
435 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
436 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
438 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
440 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
443 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
446 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
451 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
452 table->WatermarkRow[WM_DCFCL
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H A Ddcn31_smu.h74 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member in struct:__anon251
231 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member in struct:dcn31_watermarks
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/
H A Dvg_clk_mgr.c397 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
398 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
400 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
401 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
403 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
405 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
408 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
411 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
416 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
417 table->WatermarkRow[WM_DCFCL
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H A Ddcn301_smu.h77 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member in struct:__anon92
131 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member in struct:watermarks
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_clk_mgr.c447 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
448 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
450 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
451 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
453 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
455 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
458 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
461 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
466 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
467 table->WatermarkRow[WM_DCFCL
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H A Ddcn314_smu.h72 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member in struct:dcn314_watermarks
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/
H A Ddcn315_clk_mgr.c392 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
393 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
395 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
396 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
398 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
400 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
403 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
406 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
411 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
412 table->WatermarkRow[WM_DCFCL
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H A Ddcn315_smu.h90 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member in struct:dcn315_watermarks
/openbsd-current/sys/dev/pci/drm/amd/pm/powerplay/inc/
H A Dsmu10_driver_if.h70 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member in struct:__anon650
/openbsd-current/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu13_driver_if_v13_0_5.h73 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member in struct:__anon624
H A Dsmu12_driver_if.h73 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member in struct:__anon892
H A Dsmu13_driver_if_v13_0_4.h73 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member in struct:__anon613
H A Dsmu11_driver_if_vangogh.h72 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member in struct:__anon500
H A Dsmu13_driver_if_yellow_carp.h72 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member in struct:__anon717
/openbsd-current/sys/dev/pci/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_5_ppt.c416 table->WatermarkRow[WM_DCFCLK][i].MinClock =
418 table->WatermarkRow[WM_DCFCLK][i].MaxClock =
420 table->WatermarkRow[WM_DCFCLK][i].MinMclk =
422 table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
425 table->WatermarkRow[WM_DCFCLK][i].WmSetting =
430 table->WatermarkRow[WM_SOCCLK][i].MinClock =
432 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
434 table->WatermarkRow[WM_SOCCLK][i].MinMclk =
436 table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
439 table->WatermarkRow[WM_SOCCL
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H A Dsmu_v13_0_4_ppt.c672 table->WatermarkRow[WM_DCFCLK][i].MinClock =
674 table->WatermarkRow[WM_DCFCLK][i].MaxClock =
676 table->WatermarkRow[WM_DCFCLK][i].MinMclk =
678 table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
681 table->WatermarkRow[WM_DCFCLK][i].WmSetting =
686 table->WatermarkRow[WM_SOCCLK][i].MinClock =
688 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
690 table->WatermarkRow[WM_SOCCLK][i].MinMclk =
692 table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
695 table->WatermarkRow[WM_SOCCL
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H A Dyellow_carp_ppt.c507 table->WatermarkRow[WM_DCFCLK][i].MinClock =
509 table->WatermarkRow[WM_DCFCLK][i].MaxClock =
511 table->WatermarkRow[WM_DCFCLK][i].MinMclk =
513 table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
516 table->WatermarkRow[WM_DCFCLK][i].WmSetting =
521 table->WatermarkRow[WM_SOCCLK][i].MinClock =
523 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
525 table->WatermarkRow[WM_SOCCLK][i].MinMclk =
527 table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
530 table->WatermarkRow[WM_SOCCL
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/openbsd-current/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/
H A Dsmu_helper.c728 table->WatermarkRow[1][i].MinClock =
732 table->WatermarkRow[1][i].MaxClock =
736 table->WatermarkRow[1][i].MinUclk =
740 table->WatermarkRow[1][i].MaxUclk =
744 table->WatermarkRow[1][i].WmSetting = (uint8_t)
749 table->WatermarkRow[0][i].MinClock =
753 table->WatermarkRow[0][i].MaxClock =
757 table->WatermarkRow[0][i].MinUclk =
761 table->WatermarkRow[0][i].MaxUclk =
765 table->WatermarkRow[
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/openbsd-current/sys/dev/pci/drm/amd/pm/swsmu/smu12/
H A Drenoir_ppt.c1057 table->WatermarkRow[WM_DCFCLK][i].MinClock =
1059 table->WatermarkRow[WM_DCFCLK][i].MaxClock =
1061 table->WatermarkRow[WM_DCFCLK][i].MinMclk =
1063 table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
1066 table->WatermarkRow[WM_DCFCLK][i].WmSetting =
1068 table->WatermarkRow[WM_DCFCLK][i].WmType =
1073 table->WatermarkRow[WM_SOCCLK][i].MinClock =
1075 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1077 table->WatermarkRow[WM_SOCCLK][i].MinMclk =
1079 table->WatermarkRow[WM_SOCCL
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