Searched refs:WM_DCFCLK (Results 1 - 21 of 21) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/
H A Ddcn316_clk_mgr.c354 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
355 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
357 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
358 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
360 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
362 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
365 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
368 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
373 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
374 table->WatermarkRow[WM_DCFCLK][num_valid_set
[all...]
H A Ddcn316_smu.h56 WM_DCFCLK, enumerator in enum:__anon267
/openbsd-current/sys/dev/pci/drm/amd/pm/powerplay/inc/
H A Dsmu10_driver_if.h65 WM_DCFCLK, enumerator in enum:__anon649
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_clk_mgr.c432 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
433 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
435 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
436 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
438 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
440 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
443 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
446 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
451 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
452 table->WatermarkRow[WM_DCFCLK][num_valid_set
[all...]
H A Ddcn31_smu.h68 WM_DCFCLK, enumerator in enum:__anon250
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/
H A Dvg_clk_mgr.c397 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
398 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
400 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
401 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
403 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
405 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
408 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
411 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
416 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
417 table->WatermarkRow[WM_DCFCLK][num_valid_set
[all...]
H A Ddcn301_smu.h71 WM_DCFCLK, enumerator in enum:__anon91
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_clk_mgr.c447 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
448 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
450 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
451 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
453 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
455 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
458 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
461 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
466 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
467 table->WatermarkRow[WM_DCFCLK][num_valid_set
[all...]
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/
H A Ddcn315_clk_mgr.c392 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
393 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
395 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
396 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
398 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
400 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
403 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
406 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
411 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
412 table->WatermarkRow[WM_DCFCLK][num_valid_set
[all...]
H A Ddcn315_smu.h57 WM_DCFCLK, enumerator in enum:__anon263
/openbsd-current/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu13_driver_if_v13_0_5.h67 WM_DCFCLK, enumerator in enum:__anon623
H A Dsmu12_driver_if.h67 WM_DCFCLK, enumerator in enum:__anon891
H A Dsmu13_driver_if_v13_0_4.h67 WM_DCFCLK, enumerator in enum:__anon612
H A Dsmu11_driver_if_vangogh.h66 WM_DCFCLK, enumerator in enum:__anon499
H A Dsmu13_driver_if_yellow_carp.h66 WM_DCFCLK, enumerator in enum:__anon716
/openbsd-current/sys/dev/pci/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_5_ppt.c416 table->WatermarkRow[WM_DCFCLK][i].MinClock =
418 table->WatermarkRow[WM_DCFCLK][i].MaxClock =
420 table->WatermarkRow[WM_DCFCLK][i].MinMclk =
422 table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
425 table->WatermarkRow[WM_DCFCLK][i].WmSetting =
H A Dsmu_v13_0_4_ppt.c672 table->WatermarkRow[WM_DCFCLK][i].MinClock =
674 table->WatermarkRow[WM_DCFCLK][i].MaxClock =
676 table->WatermarkRow[WM_DCFCLK][i].MinMclk =
678 table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
681 table->WatermarkRow[WM_DCFCLK][i].WmSetting =
H A Dyellow_carp_ppt.c507 table->WatermarkRow[WM_DCFCLK][i].MinClock =
509 table->WatermarkRow[WM_DCFCLK][i].MaxClock =
511 table->WatermarkRow[WM_DCFCLK][i].MinMclk =
513 table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
516 table->WatermarkRow[WM_DCFCLK][i].WmSetting =
/openbsd-current/sys/dev/pci/drm/amd/pm/swsmu/smu12/
H A Drenoir_ppt.c1057 table->WatermarkRow[WM_DCFCLK][i].MinClock =
1059 table->WatermarkRow[WM_DCFCLK][i].MaxClock =
1061 table->WatermarkRow[WM_DCFCLK][i].MinMclk =
1063 table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
1066 table->WatermarkRow[WM_DCFCLK][i].WmSetting =
1068 table->WatermarkRow[WM_DCFCLK][i].WmType =
/openbsd-current/sys/dev/pci/drm/amd/pm/swsmu/smu11/
H A Dvangogh_ppt.c1646 table->WatermarkRow[WM_DCFCLK][i].MinClock =
1648 table->WatermarkRow[WM_DCFCLK][i].MaxClock =
1650 table->WatermarkRow[WM_DCFCLK][i].MinMclk =
1652 table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
1655 table->WatermarkRow[WM_DCFCLK][i].WmSetting =
/openbsd-current/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/
H A Dsmu10_hwmgr.c1365 table->WatermarkRow[WM_DCFCLK][i].WmType = (uint8_t)0;

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