Searched refs:UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK (Results 1 - 9 of 9) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/uvd/
H A Duvd_5_0_sh_mask.h767 #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x80 macro
H A Duvd_6_0_sh_mask.h765 #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x80 macro
/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h515 #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x00000080L macro
H A Dvcn_2_0_0_sh_mask.h3272 #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x00000080L macro
H A Dvcn_2_6_0_sh_mask.h3817 #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x00000080L macro
H A Dvcn_2_5_sh_mask.h2146 #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x00000080L macro
H A Dvcn_3_0_0_sh_mask.h2891 #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x00000080L macro
H A Dvcn_4_0_0_sh_mask.h3944 #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x00000080L macro
H A Dvcn_4_0_3_sh_mask.h3979 #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x00000080L macro
[all...]

Completed in 462 milliseconds