Searched refs:UPLL_FB_DIV (Results 1 - 10 of 10) sorted by relevance

/openbsd-current/sys/dev/pci/drm/radeon/
H A Drv770.c84 /* set UPLL_FB_DIV to 0x50000 */
85 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(0x50000), ~UPLL_FB_DIV_MASK);
92 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(1), ~UPLL_FB_DIV(1));
110 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div),
123 WREG32_P(CG_UPLL_FUNC_CNTL_3, 0, ~UPLL_FB_DIV(1));
H A Drv770d.h62 # define UPLL_FB_DIV(x) ((x) << 0) macro
H A Dsid.h146 # define UPLL_FB_DIV(x) ((x) << 0) macro
H A Devergreend.h367 # define UPLL_FB_DIV(x) ((x) << 0) macro
H A Dr600d.h1561 # define UPLL_FB_DIV(x) ((x) << 4) macro
H A Dr600.c257 UPLL_FB_DIV(fb_div) |
H A Devergreen.c1237 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK);
H A Dsi.c7045 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK);
/openbsd-current/sys/dev/pci/drm/amd/amdgpu/
H A Dsid.h147 # define UPLL_FB_DIV(x) ((x) << 0) macro
H A Damdgpu_si.c1824 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK);

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