Searched refs:UMC_BASE__INST5_SEG1 (Results 1 - 12 of 12) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/include/
H A Dnavi10_ip_offset.h807 #define UMC_BASE__INST5_SEG1 0 macro
H A Dvega20_ip_offset.h876 #define UMC_BASE__INST5_SEG1 0 macro
H A Dbeige_goby_ip_offset.h1212 #define UMC_BASE__INST5_SEG1 0 macro
H A Ddimgrey_cavefish_ip_offset.h987 #define UMC_BASE__INST5_SEG1 0 macro
H A Drenoir_ip_offset.h1274 #define UMC_BASE__INST5_SEG1 0 macro
H A Dnavi12_ip_offset.h1024 #define UMC_BASE__INST5_SEG1 0 macro
H A Dnavi14_ip_offset.h1024 #define UMC_BASE__INST5_SEG1 0 macro
H A Dsienna_cichlid_ip_offset.h1073 #define UMC_BASE__INST5_SEG1 0x02426C00 macro
H A Dyellow_carp_offset.h1303 #define UMC_BASE__INST5_SEG1 0 macro
H A Daldebaran_ip_offset.h1431 #define UMC_BASE__INST5_SEG1 0 macro
H A Dvangogh_ip_offset.h1384 #define UMC_BASE__INST5_SEG1 0 macro
H A Darct_ip_offset.h1461 #define UMC_BASE__INST5_SEG1 0x00154000 macro

Completed in 153 milliseconds