/openbsd-current/gnu/llvm/llvm/lib/CodeGen/ |
H A D | AggressiveAntiDepBreaker.cpp | 615 const TargetRegisterClass *SuperRC = 618 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC); 626 RenameOrder.insert(RenameOrderType::value_type(SuperRC, Order.size())); 628 unsigned OrigR = RenameOrder[SuperRC]; 721 RenameOrder.erase(SuperRC); 722 RenameOrder.insert(RenameOrderType::value_type(SuperRC, R));
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H A D | RegAllocGreedy.cpp | 1245 /// on \p MI and that are also in \p SuperRC. 1247 const MachineInstr *MI, Register Reg, const TargetRegisterClass *SuperRC, 1250 assert(SuperRC && "Invalid register class"); 1253 MI->getRegClassConstraintEffectForVReg(Reg, SuperRC, TII, TRI, 1341 const TargetRegisterClass *SuperRC = 1344 RegClassInfo.getNumAllocatableRegs(SuperRC); 1354 getNumAllocatableRegsForConstraints(MI, VirtReg.reg(), SuperRC,
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H A D | TargetLoweringBase.cpp | 1275 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); local 1277 if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC)) 1279 if (!isLegalRC(*TRI, *SuperRC)) 1281 BestRC = SuperRC;
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H A D | MachineVerifier.cpp | 2229 const TargetRegisterClass *SuperRC = local 2231 if (!SuperRC) { 2235 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
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/openbsd-current/gnu/llvm/llvm/lib/Target/AMDGPU/ |
H A D | SILoadStoreOptimizer.cpp | 1183 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); local 1184 Register DestReg = MRI->createVirtualRegister(SuperRC); 1322 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); local 1324 Register DestReg = MRI->createVirtualRegister(SuperRC); 1371 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); local 1373 Register DestReg = MRI->createVirtualRegister(SuperRC); 1421 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); local 1424 Register DestReg = MRI->createVirtualRegister(SuperRC); 1476 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); local 1479 Register DestReg = MRI->createVirtualRegister(SuperRC); 1540 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); local 1590 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); local 1638 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); local 1864 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); local [all...] |
H A D | SIRegisterInfo.h | 249 /// Returns a register class which is compatible with \p SuperRC, such that a 254 getCompatibleSubRegClass(const TargetRegisterClass *SuperRC,
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H A D | SIInstrInfo.h | 71 const TargetRegisterClass *SuperRC, 77 const TargetRegisterClass *SuperRC,
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H A D | SIRegisterInfo.cpp | 2816 SIRegisterInfo::getCompatibleSubRegClass(const TargetRegisterClass *SuperRC, argument 2821 getMatchingSuperRegClass(SuperRC, SubRC, SubIdx); 2822 return MatchRC && MatchRC->hasSubClassEq(SuperRC) ? MatchRC : nullptr;
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H A D | SIInstrInfo.cpp | 4997 const TargetRegisterClass *SuperRC, 5015 Register NewSuperReg = MRI.createVirtualRegister(SuperRC); 5030 const TargetRegisterClass *SuperRC, 5042 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC, 5071 const TargetRegisterClass *SuperRC = RI.getLargestLegalSuperClass(RC, *MF); 5072 if (!SuperRC) 5075 DRC = RI.getMatchingSuperRegClass(SuperRC, DRC, MO.getSubReg());
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H A D | AMDGPUISelDAGToDAG.cpp | 379 const TargetRegisterClass *SuperRC = local 384 return Subtarget->getRegisterInfo()->getSubClassWithSubReg(SuperRC,
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H A D | AMDGPUInstructionSelector.cpp | 2898 const TargetRegisterClass *SuperRC, Register IdxReg, 2912 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(SuperRC, EltSize); 2897 computeIndirectRegIndex(MachineRegisterInfo &MRI, const SIRegisterInfo &TRI, const TargetRegisterClass *SuperRC, Register IdxReg, unsigned EltSize, GISelKnownBits &KnownBits) argument
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H A D | SIISelLowering.cpp | 3761 const TargetRegisterClass *SuperRC, 3764 int NumElts = TRI.getRegSizeInBits(*SuperRC) / 32; 3760 computeIndirectRegAndOffset(const SIRegisterInfo &TRI, const TargetRegisterClass *SuperRC, unsigned VecReg, int Offset) argument
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/openbsd-current/gnu/llvm/llvm/lib/Target/Hexagon/ |
H A D | HexagonRegisterInfo.cpp | 439 if (const TargetRegisterClass *SuperRC = *RC.getSuperClasses()) 440 return getHexagonSubRegIndex(*SuperRC, GenIdx);
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H A D | HexagonCopyToCombine.cpp | 583 const TargetRegisterClass *SuperRC = nullptr; local 585 SuperRC = &Hexagon::DoubleRegsRegClass; 589 SuperRC = &Hexagon::HvxWRRegClass; 595 unsigned DoubleRegDest = TRI->getMatchingSuperReg(LoRegDef, SubLo, SuperRC);
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/openbsd-current/gnu/llvm/llvm/utils/TableGen/ |
H A D | CodeGenRegisters.h | 315 // classes SuperRC such that: 317 // R:SubRegIndex in this RC for all R in SuperRC. 411 CodeGenRegisterClass *SuperRC) { 412 SuperRegClasses[SubIdx].insert(SuperRC); 410 addSuperRegClass(CodeGenSubRegIndex *SubIdx, CodeGenRegisterClass *SuperRC) argument
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/openbsd-current/gnu/llvm/llvm/include/llvm/CodeGen/ |
H A D | TargetRegisterInfo.h | 169 /// There exists SuperRC where: 170 /// For all Reg in SuperRC: 642 /// \p SuperRC at \p SubRegIdx. 644 getSubRegisterClass(const TargetRegisterClass *SuperRC, 731 /// Find a register class, SuperRC and two sub-register indices, PreA and 736 /// 2. For all Reg in SuperRC: Reg:PreA in RCA and Reg:PreB in RCB, and 738 /// 3. SuperRC->getSize() >= max(RCA->getSize(), RCB->getSize()). 740 /// SuperRC will be chosen such that no super-class of SuperRC satisfies the 1170 // corresponds to a SuperRC suc [all...] |