Searched refs:SUBBLK_RESET_CR (Results 1 - 1 of 1) sorted by relevance

/openbsd-current/sys/arch/riscv64/dev/
H A Dmpfclock.c44 #define SUBBLK_RESET_CR 0x0088 macro
66 #define CLK_RESERVED 20 /* FPGA in SUBBLK_RESET_CR */
214 val = HREAD4(sc, SUBBLK_RESET_CR);
216 HWRITE4(sc, SUBBLK_RESET_CR, val);
218 val = HREAD4(sc, SUBBLK_RESET_CR);
220 HWRITE4(sc, SUBBLK_RESET_CR, val);

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