Searched refs:SOFT_REGISTERS_TABLE_15__DisplayPhy6Config__SHIFT (Results 1 - 5 of 5) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/smu/
H A Dsmu_7_1_1_sh_mask.h2718 #define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config__SHIFT 0x10 macro
H A Dsmu_7_1_0_sh_mask.h3580 #define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config__SHIFT 0x10 macro
H A Dsmu_7_1_2_sh_mask.h3744 #define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config__SHIFT 0x10 macro
H A Dsmu_7_0_1_sh_mask.h3584 #define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config__SHIFT 0x10 macro
H A Dsmu_7_1_3_sh_mask.h3412 #define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config__SHIFT 0x10 macro

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