Searched refs:SIMM8 (Results 1 - 8 of 8) sorted by relevance

/openbsd-current/gnu/usr.bin/binutils/opcodes/
H A Dm10300-opc.c176 #define SIMM8 (SD8N_SHIFT8+1)
180 #define SIMM16 (SIMM8+1)
447 { "mov", 0x8000, 0xf000, 0, FMT_S1, 0, {SIMM8, DN01}},
528 { "mov", 0xfb6a0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}},
529 { "mov", 0xfb7a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}},
563 { "mov", 0xfb080000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}},
590 { "mac", 0xfb0b0000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}},
600 { "macb", 0xfb2b0000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}},
610 { "mach", 0xfb4b0000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}},
729 { "movhu", 0xfbea0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN
175 #define SIMM8 macro
[all...]
H A Dm10200-opc.c118 #define SIMM8 (SD8N_PCREL+1)
122 #define SIMM16 (SIMM8+1)
164 { "mov", 0x8000, 0xf000, FMT_2, {SIMM8, DN01}},
244 { "add", 0xd400, 0xfc00, FMT_2, {SIMM8, DN0}},
247 { "add", 0xd000, 0xfc00, FMT_2, {SIMM8, AN0}},
251 { "addnf", 0xf50c00, 0xfffc00, FMT_5, {SIMM8, AN0}},
272 { "cmp", 0xd800, 0xfc00, FMT_2, {SIMM8, DN0}},
117 #define SIMM8 macro
H A Dm32r-opc.c287 { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
635 { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
1630 { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
H A Dm32r-opinst.c78 { INPUT, "simm8", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM8), 0, 0 },
291 { INPUT, "simm8", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM8), 0, 0 },
/openbsd-current/gnu/usr.bin/binutils-2.17/opcodes/
H A Dm10300-opc.c177 #define SIMM8 (SD8N_SHIFT8+1)
181 #define SIMM16 (SIMM8+1)
448 { "mov", 0x8000, 0xf000, 0, FMT_S1, 0, {SIMM8, DN01}},
529 { "mov", 0xfb6a0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}},
530 { "mov", 0xfb7a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}},
564 { "mov", 0xfb080000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}},
591 { "mac", 0xfb0b0000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}},
601 { "macb", 0xfb2b0000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}},
611 { "mach", 0xfb4b0000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}},
730 { "movhu", 0xfbea0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN
176 #define SIMM8 macro
[all...]
H A Dm10200-opc.c118 #define SIMM8 (SD8N_PCREL+1)
122 #define SIMM16 (SIMM8+1)
164 { "mov", 0x8000, 0xf000, FMT_2, {SIMM8, DN01}},
244 { "add", 0xd400, 0xfc00, FMT_2, {SIMM8, DN0}},
247 { "add", 0xd000, 0xfc00, FMT_2, {SIMM8, AN0}},
251 { "addnf", 0xf50c00, 0xfffc00, FMT_5, {SIMM8, AN0}},
272 { "cmp", 0xd800, 0xfc00, FMT_2, {SIMM8, DN0}},
117 #define SIMM8 macro
H A Dm32r-opinst.c78 { INPUT, "simm8", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM8), 0, 0 },
291 { INPUT, "simm8", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM8), 0, 0 },
H A Dm32r-opc.c285 { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
633 { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
1628 { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },

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