Searched refs:SEW (Results 1 - 7 of 7) sorted by relevance

/openbsd-current/gnu/llvm/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVBaseInfo.cpp133 // 5:3 | vsew[2:0] | Standard element width (SEW) setting
135 unsigned RISCVVType::encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, argument
137 assert(isValidSEW(SEW) && "Invalid SEW");
139 unsigned VSEWBits = encodeSEW(SEW);
190 unsigned RISCVVType::getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul) { argument
198 assert(SEW >= 8 && "Unexpected SEW value");
199 return (SEW * 8) / LMul;
H A DRISCVBaseInfo.h71 // Does this instruction have a SEW operand. It will be the last explicit
158 /// \returns true if there is a SEW operand for the instruction.
188 // instructions with VL also have SEW.
418 // Is this a SEW value that can be encoded into the VTYPE format.
419 inline static bool isValidSEW(unsigned SEW) { argument
420 return isPowerOf2_32(SEW) && SEW >= 8 && SEW <= 1024;
428 unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic,
450 inline static unsigned encodeSEW(unsigned SEW) {
[all...]
/openbsd-current/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVInsertVSETVLI.cpp89 /// not a load or store which ignores SEW.
134 bool SEW = false; member in struct:__anon3066::DemandedFields
142 return SEW || LMUL || SEWLMULRatio || TailPolicy || MaskPolicy;
152 SEW = true;
177 OS << "SEW=" << SEW << ", "; local
202 if (Used.SEW &&
232 // that it can't use the value of a SEW, VL, or Policy operand as they might
254 // Loads and stores with implicit EEW do not demand SEW or LMUL directly.
256 // EMUL, but which allows us the flexibility to change SEW an
307 uint8_t SEW = 0; member in class:__anon3066::VSETVLIInfo
683 unsigned SEW = Log2SEW ? 1 << Log2SEW : 8; local
1139 unsigned SEW = Info.getSEW(); local
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H A DRISCVISelDAGToDAG.cpp557 unsigned SEW =
562 unsigned VTypeI = RISCVVType::encodeVTYPE(VLMul, SEW, /*TailAgnostic*/ true,
1153 SDValue SEW = CurDAG->getTargetConstant(
1160 ReplaceNode(Node, CurDAG->getMachineNode(VMSetOpcode, DL, VT, VL, SEW));
1167 CurDAG->getMachineNode(VMSLTOpcode, DL, VT, {Src1, Src2, VL, SEW}),
1170 {Cmp, Cmp, VL, SEW}));
1232 SDValue SEW = CurDAG->getTargetConstant(
1259 CurDAG->getMachineNode(VMSLTOpcode, DL, VT, {Src1, Src2, VL, SEW}),
1279 {MaskedOff, Src1, Src2, V0, VL, SEW, Glue}),
1826 SDValue SEW
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H A DRISCVInstrInfo.cpp181 // If SEW is different, return false.
419 MIB.add(DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc))); // SEW
450 MIB.add(DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc))); // SEW
1710 ErrInfo = "VL operand w/o SEW operand?";
1718 ErrInfo = "Unexpected SEW value";
1721 unsigned SEW = Log2SEW ? 1 << Log2SEW : 8; local
1722 if (!RISCVVType::isValidSEW(SEW)) {
1723 ErrInfo = "Unexpected SEW value";
2026 // Print the full VType operand of vsetvli/vsetivli instructions, and the SEW
2038 unsigned SEW local
2040 OS << "e" << SEW; local
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H A DRISCVISelLowering.cpp1841 // each fractional LMUL we support SEW between 8 and LMUL*ELEN.
3211 // If this is SEW=64 on RV32, use a strided load with a stride of x0.
4894 // Custom-lower a SPLAT_VECTOR_PARTS where XLEN<SEW, as the SEW element type is
5078 // RVV only has truncates which operate from SEW*2->SEW, so lower arbitrary
5464 // that a widening operation never uses SEW=64.
5475 // instruction to sign-extend since SEW>XLEN.
5499 // Double the VL since we halved SEW.
5524 SDValue SEW local
5539 SDValue SEW = DAG.getConstant(Sew, DL, XLenVT); local
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/openbsd-current/gnu/llvm/clang/lib/CodeGen/
H A DCGDebugInfo.cpp772 unsigned SEW = CGM.getContext().getTypeSize(Info.ElementType); local
776 unsigned FixedSize = ElementCount * SEW;
788 // Element count = (VLENB / SEW) x LMUL
797 SEW / 8, // SEW is in bits.

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