Searched refs:SDMA0_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT (Results 1 - 5 of 5) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_2_2_sh_mask.h2851 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 macro
H A Dsdma0_4_2_sh_mask.h2841 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 macro
/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/sdma/
H A Dsdma_4_4_0_sh_mask.h2677 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 macro
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/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_sh_mask.h2639 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 macro
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H A Dgc_10_3_0_sh_mask.h2738 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 macro
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