Searched refs:SDMA0_QUEUE5_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT (Results 1 - 2 of 2) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_11_0_3_sh_mask.h2026 #define SDMA0_QUEUE5_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb macro
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H A Dgc_11_0_0_sh_mask.h1969 #define SDMA0_QUEUE5_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb macro
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