Searched refs:SDMA0_BASE__INST5_SEG0 (Results 1 - 7 of 7) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/include/
H A Dvega20_ip_offset.h707 #define SDMA0_BASE__INST5_SEG0 0 macro
H A Dbeige_goby_ip_offset.h1064 #define SDMA0_BASE__INST5_SEG0 0 macro
H A Drenoir_ip_offset.h1147 #define SDMA0_BASE__INST5_SEG0 0 macro
H A Dsienna_cichlid_ip_offset.h904 #define SDMA0_BASE__INST5_SEG0 0 macro
H A Dyellow_carp_offset.h1155 #define SDMA0_BASE__INST5_SEG0 0 macro
H A Daldebaran_ip_offset.h1234 #define SDMA0_BASE__INST5_SEG0 0 macro
H A Darct_ip_offset.h953 #define SDMA0_BASE__INST5_SEG0 0 macro

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