/openbsd-current/gnu/llvm/llvm/lib/Target/RISCV/MCTargetDesc/ |
H A D | RISCVELFObjectWriter.cpp | 1 //===-- RISCVELFObjectWriter.cpp - RISCV ELF Writer -----------------------===// 65 case RISCV::fixup_riscv_pcrel_hi20: 67 case RISCV::fixup_riscv_pcrel_lo12_i: 69 case RISCV::fixup_riscv_pcrel_lo12_s: 71 case RISCV::fixup_riscv_got_hi20: 73 case RISCV::fixup_riscv_tls_got_hi20: 75 case RISCV::fixup_riscv_tls_gd_hi20: 77 case RISCV::fixup_riscv_jal: 79 case RISCV::fixup_riscv_branch: 81 case RISCV [all...] |
H A D | RISCVMCObjectFileInfo.cpp | 1 //===-- RISCVMCObjectFileInfo.cpp - RISCV object file properties ----------===// 22 return (STI->hasFeature(RISCV::FeatureStdExtC) || 23 STI->hasFeature(RISCV::FeatureExtZca))
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H A D | RISCVMatInt.cpp | 24 case RISCV::SLLI: 25 case RISCV::SRLI: 28 case RISCV::ADDI: 29 case RISCV::ADDIW: 30 case RISCV::LUI: 51 bool IsRV64 = ActiveFeatures[RISCV::Feature64Bit]; 54 if (ActiveFeatures[RISCV::FeatureStdExtZbs] && isPowerOf2_64(Val) && 56 Res.emplace_back(RISCV::BSETI, Log2_64(Val)); 72 Res.emplace_back(RISCV::LUI, Hi20); 75 unsigned AddiOpc = (IsRV64 && Hi20) ? RISCV [all...] |
H A D | RISCVAsmBackend.cpp | 1 //===-- RISCVAsmBackend.cpp - RISCV Assembler Backend ---------------------===// 35 #include "llvm/BinaryFormat/ELFRelocs/RISCV.def" 97 static_assert((std::size(Infos)) == RISCV::NumTargetFixupKinds, 131 case RISCV::fixup_riscv_got_hi20: 132 case RISCV::fixup_riscv_tls_got_hi20: 133 case RISCV::fixup_riscv_tls_gd_hi20: 137 return STI.getFeatureBits()[RISCV::FeatureRelax] || ForceRelocs; 157 case RISCV::fixup_riscv_rvc_branch: 161 case RISCV::fixup_riscv_rvc_jump: 174 case RISCV [all...] |
H A D | RISCVMCCodeEmitter.cpp | 1 //===-- RISCVMCCodeEmitter.cpp - Convert RISCV code to machine code -------===// 97 // meaning AUIPC and JALR won't go through RISCV MC to MC compressed 109 if (MI.getOpcode() == RISCV::PseudoTAIL) { 111 Ra = RISCV::X6; 112 } else if (MI.getOpcode() == RISCV::PseudoCALLReg) { 115 } else if (MI.getOpcode() == RISCV::PseudoCALL) { 117 Ra = RISCV::X1; 118 } else if (MI.getOpcode() == RISCV::PseudoJump) { 129 TmpInst = MCInstBuilder(RISCV::AUIPC).addReg(Ra).addExpr(CallExpr); 133 if (MI.getOpcode() == RISCV [all...] |
H A D | RISCVFixupKinds.h | 1 //===-- RISCVFixupKinds.h - RISCV Specific Fixup Entries --------*- C++ -*-===// 14 #undef RISCV macro 16 namespace llvm::RISCV { namespace in class:llvm 111 } // end namespace llvm::RISCV
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/openbsd-current/gnu/llvm/llvm/lib/Target/RISCV/ |
H A D | RISCVSExtWRemoval.cpp | 15 #include "RISCV.h" 50 StringRef getPassName() const override { return "RISCV sext.w Removal"; } 56 INITIALIZE_PASS(RISCVSExtWRemoval, DEBUG_TYPE, "RISCV sext.w Removal", false, 76 case RISCV::SRAI: 78 case RISCV::SRLI: 81 case RISCV::ADDI: 82 return MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == RISCV::X0; 84 case RISCV::ANDI: 87 case RISCV::ORI: 90 case RISCV [all...] |
H A D | RISCVAsmPrinter.cpp | 1 //===-- RISCVAsmPrinter.cpp - RISCV LLVM assembly writer ------------------===// 10 // of machine-dependent LLVM code to the RISCV assembly language. 17 #include "RISCV.h" 56 StringRef getPassName() const override { return "RISCV Assembly Printer"; } 113 case RISCV::HWASAN_CHECK_MEMACCESS_SHORTGRANULES: 139 OS << RISCVInstPrinter::getRegisterName(RISCV::X0); 252 std::string SymName = "__hwasan_check_x" + utostr(Reg - RISCV::X0) + "_" + 259 EmitToStreamer(*OutStreamer, MCInstBuilder(RISCV::PseudoCALL).addExpr(Expr)); 304 MCInstBuilder(RISCV::SLLI).addReg(RISCV [all...] |
H A D | RISCVRegisterInfo.cpp | 1 //===-- RISCVRegisterInfo.cpp - RISCV Register Information ------*- C++ -*-===// 9 // This file contains the RISCV implementation of the TargetRegisterInfo class. 14 #include "RISCV.h" 38 static_assert(RISCV::X1 == RISCV::X0 + 1, "Register list not consecutive"); 39 static_assert(RISCV::X31 == RISCV::X0 + 31, "Register list not consecutive"); 40 static_assert(RISCV::F1_H == RISCV::F0_H + 1, "Register list not consecutive"); 41 static_assert(RISCV [all...] |
H A D | RISCVMakeCompressible.cpp | 68 #include "RISCV.h" 78 #define RISCV_COMPRESS_INSTRS_NAME "RISCV Make Compressible" 104 case RISCV::LW: 105 case RISCV::SW: 106 case RISCV::FLW: 107 case RISCV::FSW: 109 case RISCV::LD: 110 case RISCV::SD: 111 case RISCV::FLD: 112 case RISCV [all...] |
H A D | RISCVExpandPseudoInsts.cpp | 15 #include "RISCV.h" 26 #define RISCV_EXPAND_PSEUDO_NAME "RISCV pseudo instruction expansion pass" 27 #define RISCV_PRERA_EXPAND_PSEUDO_NAME "RISCV Pre-RA pseudo instruction expansion pass" 85 case RISCV::PseudoCCMOVGPR: 86 case RISCV::PseudoCCADD: 87 case RISCV::PseudoCCSUB: 88 case RISCV::PseudoCCAND: 89 case RISCV::PseudoCCOR: 90 case RISCV::PseudoCCXOR: 91 case RISCV [all...] |
H A D | RISCVInstrInfo.cpp | 1 //===-- RISCVInstrInfo.cpp - RISCV Instruction Information ------*- C++ -*-===// 9 // This file contains the RISCV implementation of the TargetInstrInfo class. 15 #include "RISCV.h" 49 using namespace RISCV; 57 : RISCVGenInstrInfo(RISCV::ADJCALLSTACKDOWN, RISCV::ADJCALLSTACKUP), 62 return MCInstBuilder(RISCV::C_NOP); 63 return MCInstBuilder(RISCV::ADDI) 64 .addReg(RISCV::X0) 65 .addReg(RISCV [all...] |
H A D | RISCVMergeBaseOffset.cpp | 14 #include "RISCV.h" 26 #define RISCV_MERGE_BASE_OFFSET_NAME "RISCV Merge Base Offset" 91 if (Hi.getOpcode() != RISCV::LUI && Hi.getOpcode() != RISCV::AUIPC) 96 Hi.getOpcode() == RISCV::AUIPC ? RISCVII::MO_PCREL_HI : RISCVII::MO_HI; 108 if (Lo->getOpcode() != RISCV::ADDI) 112 if (Hi.getOpcode() == RISCV::LUI) { 117 assert(Hi.getOpcode() == RISCV::AUIPC); 143 if (Hi.getOpcode() != RISCV::AUIPC) 176 assert((TailAdd.getOpcode() == RISCV [all...] |
H A D | RISCVStripWSuffix.cpp | 17 #include "RISCV.h" 43 StringRef getPassName() const override { return "RISCV Strip W Suffix"; } 50 "RISCV Strip W Suffix", false, false) 73 case RISCV::ADDW: 74 case RISCV::SLLIW: 77 MI.getOpcode() == RISCV::ADDW ? RISCV::ADD : RISCV::SLLI;
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H A D | RISCVMacroFusion.cpp | 1 //===- RISCVMacroFusion.cpp - RISCV Macro Fusion --------------------------===// 9 /// \file This file contains the RISCV implementation of the DAG scheduling 27 if (SecondMI.getOpcode() != RISCV::ADDI && 28 SecondMI.getOpcode() != RISCV::ADDIW) 35 if (FirstMI->getOpcode() != RISCV::LUI)
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H A D | RISCVMCInstLower.cpp | 1 //===-- RISCVMCInstLower.cpp - Convert RISCV MachineInstr to an MCInst ------=// 9 // This file contains code to lower RISCV MachineInstrs to their corresponding 14 #include "RISCV.h" 165 bool hasVLOutput = RISCV::isFaultFirstLoad(*MI); 185 if (RISCV::VRM2RegClass.contains(Reg) || 186 RISCV::VRM4RegClass.contains(Reg) || 187 RISCV::VRM8RegClass.contains(Reg)) { 188 Reg = TRI->getSubReg(Reg, RISCV::sub_vrm1_0); 190 } else if (RISCV::FPR16RegClass.contains(Reg)) { 191 Reg = TRI->getMatchingSuperReg(Reg, RISCV [all...] |
H A D | RISCVExpandAtomicPseudoInsts.cpp | 16 #include "RISCV.h" 27 "RISCV atomic pseudo instruction expansion pass" 93 case RISCV::PseudoAtomicLoadNand32: 96 case RISCV::PseudoAtomicLoadNand64: 99 case RISCV::PseudoMaskedAtomicSwap32: 102 case RISCV::PseudoMaskedAtomicLoadAdd32: 104 case RISCV::PseudoMaskedAtomicLoadSub32: 106 case RISCV::PseudoMaskedAtomicLoadNand32: 109 case RISCV::PseudoMaskedAtomicLoadMax32: 112 case RISCV [all...] |
/openbsd-current/gnu/usr.bin/clang/libLLVMRISCVAsmParser/ |
H A D | Makefile | 6 CPPFLAGS+= -I${.OBJDIR}/../include/llvm/RISCV \ 7 -I${LLVM_SRCS}/lib/Target/RISCV 11 .PATH: ${.CURDIR}/../../../llvm/llvm/lib/Target/RISCV/AsmParser
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/openbsd-current/gnu/usr.bin/clang/libLLVMRISCVDisassembler/ |
H A D | Makefile | 6 CPPFLAGS+= -I${.OBJDIR}/../include/llvm/RISCV \ 7 -I${LLVM_SRCS}/lib/Target/RISCV 11 .PATH: ${.CURDIR}/../../../llvm/llvm/lib/Target/RISCV/Disassembler
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/openbsd-current/gnu/usr.bin/clang/libLLVMRISCVInfo/ |
H A D | Makefile | 6 CPPFLAGS+= -I${.OBJDIR}/../include/llvm/RISCV \ 7 -I${LLVM_SRCS}/lib/Target/RISCV 11 .PATH: ${.CURDIR}/../../../llvm/llvm/lib/Target/RISCV/TargetInfo
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/openbsd-current/gnu/usr.bin/clang/include/llvm/RISCV/ |
H A D | Makefile | 29 RISCVGenRegisterInfo.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td 31 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \ 34 RISCVGenDisassemblerTables.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td 36 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \ 39 RISCVGenInstrInfo.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td 41 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \ 44 RISCVGenAsmWriter.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISC [all...] |
/openbsd-current/gnu/usr.bin/clang/include/llvm/TargetParser/ |
H A D | Makefile | 17 RISCVTargetParserDef.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td 19 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \
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/openbsd-current/gnu/usr.bin/clang/libLLVMRISCVDesc/ |
H A D | Makefile | 6 CPPFLAGS+= -I${.OBJDIR}/../include/llvm/RISCV \ 7 -I${LLVM_SRCS}/lib/Target/RISCV 22 .PATH: ${.CURDIR}/../../../llvm/llvm/lib/Target/RISCV/MCTargetDesc
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/openbsd-current/gnu/usr.bin/clang/libLLVMRISCVCodeGen/ |
H A D | Makefile | 6 CPPFLAGS+= -I${.OBJDIR}/../include/llvm/RISCV \ 7 -I${LLVM_SRCS}/lib/Target/RISCV 39 .PATH: ${.CURDIR}/../../../llvm/llvm/lib/Target/RISCV 40 .PATH: ${.CURDIR}/../../../llvm/llvm/lib/Target/RISCV/GISel
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/openbsd-current/gnu/llvm/llvm/lib/Target/RISCV/AsmParser/ |
H A D | RISCVAsmParser.cpp | 1 //===-- RISCVAsmParser.cpp - Parse RISCV assembly to MCInst instructions --===// 52 extern const SubtargetFeatureKV RISCVFeatureKV[RISCV::NumSubtargetFeatures]; 69 bool isRV64() const { return getSTI().hasFeature(RISCV::Feature64Bit); } 70 bool isRV32E() const { return getSTI().hasFeature(RISCV::FeatureRV32E); } 248 !getSTI().getFeatureBits()[RISCV::FeatureStdExtF]) { 253 !getSTI().getFeatureBits()[RISCV::FeatureStdExtD]) { 344 return Kind == KindTy::Register && Reg.RegNum == RISCV::V0; 352 RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg.RegNum); 360 return isGPR() && IsGPRAsFPR && !IsRV64 && !((Reg.RegNum - RISCV::X0) & 1); 998 assert(Reg >= RISCV [all...] |