| /openbsd-current/sys/dev/pci/drm/amd/display/dmub/src/ |
| H A D | dmub_dcn301.c | 36 #define REGS dmub->regs macro
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| H A D | dmub_dcn302.c | 36 #define REGS dmub->regs macro
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| H A D | dmub_dcn303.c | 18 #define REGS dmub->regs macro
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| H A D | dmub_dcn21.c | 36 #define REGS dmub->regs macro
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| H A D | dmub_dcn315.c | 42 #define REGS dmub->regs_dcn31 macro
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| H A D | dmub_dcn316.c | 42 #define REGS dmub->regs_dcn31 macro
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| H A D | dmub_dcn314.c | 42 #define REGS dmub->regs_dcn31 macro
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| H A D | dmub_reg.h | 43 #define REG(reg) (REGS)->offset.reg
45 #define FD(reg_field) (REGS)->shift.reg_field, (REGS)->mask.reg_field
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| H A D | dmub_dcn30.c | 37 #define REGS dmub->regs macro
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| H A D | dmub_dcn20.c | 37 #define REGS dmub->regs macro
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| H A D | dmub_dcn32.c | 37 #define REGS dmub->regs_dcn32 macro
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| H A D | dmub_dcn31.c | 36 #define REGS dmub->regs_dcn31 macro
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| /openbsd-current/gnu/usr.bin/gcc/gcc/config/i370/ |
| H A D | i370.h | 762 #define COUNT_REGS(X, REGS, FAIL) \
764 if (REG_OK_FOR_BASE_P (X)) REGS += 1; \
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| /openbsd-current/gnu/usr.bin/binutils/opcodes/ |
| H A D | m10300-opc.c | 213 #define REGS (REGS_SHIFT8+1)
217 #define USP (REGS+1)
755 { "movm", 0xce00, 0xff00, 0, FMT_S1, 0, {MEM(SP), REGS}},
756 { "movm", 0xcf00, 0xff00, 0, FMT_S1, 0, {REGS, MEM(SP)}},
757 { "movm", 0xf8ce00, 0xffff00, 0, FMT_D1, AM33, {MEM(USP), REGS}},
758 { "movm", 0xf8cf00, 0xffff00, 0, FMT_D1, AM33, {REGS, MEM(USP)}},
1009 { "call", 0xcd000000, 0xff000000, 0, FMT_S4, 0, {D16_SHIFT,REGS,IMM8E}},
212 #define REGS macro
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| /openbsd-current/gnu/usr.bin/binutils-2.17/opcodes/ |
| H A D | m10300-opc.c | 214 #define REGS (REGS_SHIFT8+1)
218 #define USP (REGS+1)
756 { "movm", 0xce00, 0xff00, 0, FMT_S1, 0, {MEM(SP), REGS}},
757 { "movm", 0xcf00, 0xff00, 0, FMT_S1, 0, {REGS, MEM(SP)}},
758 { "movm", 0xf8ce00, 0xffff00, 0, FMT_D1, AM33, {MEM(USP), REGS}},
759 { "movm", 0xf8cf00, 0xffff00, 0, FMT_D1, AM33, {REGS, MEM(USP)}},
1010 { "call", 0xcd000000, 0xff000000, 0, FMT_S4, 0, {D16_SHIFT,REGS,IMM8E}},
213 #define REGS macro
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| /openbsd-current/sys/dev/pci/drm/amd/amdgpu/ |
| H A D | amdgpu_uvd_v4_2.c | 635 WREG32_FIELD(UVD_CGC_GATE, REGS, 0);
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| H A D | amdgpu_uvd_v3_1.c | 211 WREG32_FIELD(UVD_CGC_GATE, REGS, 0);
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