/openbsd-current/gnu/llvm/compiler-rt/lib/xray/ |
H A D | xray_trampoline_AArch64.S | 29 STP Q6, Q7, [SP, #-32]! 49 LDP Q6, Q7, [SP], #32 82 STP Q6, Q7, [SP, #-32]! 101 LDP Q6, Q7, [SP], #32 135 STP Q6, Q7, [SP, #-32]! 152 LDP Q6, Q7, [SP], #32
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/openbsd-current/lib/libm/src/ld128/ |
H A D | s_expm1l.c | 81 Q7 = -8.802340681794263968892934703309274564037E1L, variable 147 + Q7) * x
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H A D | s_log1pl.c | 85 Q7 = 2.248234257620569139969141618556349415120E5L, variable 233 + Q7) * x
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/openbsd-current/lib/libm/src/ |
H A D | b_tgamma.c | 104 #define Q7 9.35021023573788935372153030556e-05 macro 271 q = Q0 +z*(Q1+z*(Q2+z*(Q3+z*(Q4+z*(Q5+z*(Q6+z*(Q7+z*Q8)))))));
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/openbsd-current/gnu/llvm/llvm/lib/Target/AArch64/ |
H A D | AArch64CallingConvention.cpp | 37 AArch64::Q6, AArch64::Q7};
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H A D | AArch64PBQPRegAlloc.cpp | 82 case AArch64::Q7:
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H A D | AArch64FastISel.cpp | 2971 AArch64::Q5, AArch64::Q6, AArch64::Q7 }
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H A D | AArch64ISelLowering.cpp | 6741 AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7};
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/openbsd-current/gnu/llvm/llvm/lib/Target/Sparc/Disassembler/ |
H A D | SparcDisassembler.cpp | 98 SP::Q7, SP::Q15, ~0U, ~0U } ;
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/openbsd-current/gnu/llvm/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64MCTargetDesc.cpp | 209 {codeview::RegisterId::ARM64_Q7, AArch64::Q7},
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H A D | AArch64InstPrinter.cpp | 1498 case AArch64::Q6: Reg = AArch64::Q7; break; 1499 case AArch64::Q7: Reg = AArch64::Q8; break;
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/openbsd-current/gnu/llvm/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMMCTargetDesc.cpp | 320 {codeview::RegisterId::ARM_NQ7, ARM::Q7},
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H A D | ARMMCCodeEmitter.cpp | 572 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
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/openbsd-current/gnu/llvm/llvm/lib/Target/VE/Disassembler/ |
H A D | VEDisassembler.cpp | 93 VE::Q0, VE::Q1, VE::Q2, VE::Q3, VE::Q4, VE::Q5, VE::Q6, VE::Q7,
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/openbsd-current/gnu/llvm/llvm/lib/Target/ARM/ |
H A D | ARMExpandPseudoInsts.cpp | 1151 if ((Reg >= ARM::Q0 && Reg <= ARM::Q7) || 1158 if (Reg >= ARM::Q0 && Reg <= ARM::Q7) { 1407 ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7}) 1501 ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7}) 1669 if ((Reg >= ARM::Q0 && Reg <= ARM::Q7) ||
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/openbsd-current/gnu/llvm/llvm/lib/Target/Sparc/AsmParser/ |
H A D | SparcAsmParser.cpp | 176 Sparc::Q4, Sparc::Q5, Sparc::Q6, Sparc::Q7,
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/openbsd-current/gnu/llvm/llvm/lib/Target/VE/AsmParser/ |
H A D | VEAsmParser.cpp | 127 VE::Q0, VE::Q1, VE::Q2, VE::Q3, VE::Q4, VE::Q5, VE::Q6, VE::Q7,
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/openbsd-current/gnu/llvm/llvm/lib/Target/ARM/Disassembler/ |
H A D | ARMDisassembler.cpp | 1570 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1590 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
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/openbsd-current/gnu/llvm/llvm/lib/Target/AArch64/AsmParser/ |
H A D | AArch64AsmParser.cpp | 2551 .Case("v7", AArch64::Q7)
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