Searched refs:Q7 (Results 1 - 19 of 19) sorted by relevance

/openbsd-current/gnu/llvm/compiler-rt/lib/xray/
H A Dxray_trampoline_AArch64.S29 STP Q6, Q7, [SP, #-32]!
49 LDP Q6, Q7, [SP], #32
82 STP Q6, Q7, [SP, #-32]!
101 LDP Q6, Q7, [SP], #32
135 STP Q6, Q7, [SP, #-32]!
152 LDP Q6, Q7, [SP], #32
/openbsd-current/lib/libm/src/ld128/
H A Ds_expm1l.c81 Q7 = -8.802340681794263968892934703309274564037E1L, variable
147 + Q7) * x
H A Ds_log1pl.c85 Q7 = 2.248234257620569139969141618556349415120E5L, variable
233 + Q7) * x
/openbsd-current/lib/libm/src/
H A Db_tgamma.c104 #define Q7 9.35021023573788935372153030556e-05 macro
271 q = Q0 +z*(Q1+z*(Q2+z*(Q3+z*(Q4+z*(Q5+z*(Q6+z*(Q7+z*Q8)))))));
/openbsd-current/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64CallingConvention.cpp37 AArch64::Q6, AArch64::Q7};
H A DAArch64PBQPRegAlloc.cpp82 case AArch64::Q7:
H A DAArch64FastISel.cpp2971 AArch64::Q5, AArch64::Q6, AArch64::Q7 }
H A DAArch64ISelLowering.cpp6741 AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7};
/openbsd-current/gnu/llvm/llvm/lib/Target/Sparc/Disassembler/
H A DSparcDisassembler.cpp98 SP::Q7, SP::Q15, ~0U, ~0U } ;
/openbsd-current/gnu/llvm/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCTargetDesc.cpp209 {codeview::RegisterId::ARM64_Q7, AArch64::Q7},
H A DAArch64InstPrinter.cpp1498 case AArch64::Q6: Reg = AArch64::Q7; break;
1499 case AArch64::Q7: Reg = AArch64::Q8; break;
/openbsd-current/gnu/llvm/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCTargetDesc.cpp320 {codeview::RegisterId::ARM_NQ7, ARM::Q7},
H A DARMMCCodeEmitter.cpp572 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
/openbsd-current/gnu/llvm/llvm/lib/Target/VE/Disassembler/
H A DVEDisassembler.cpp93 VE::Q0, VE::Q1, VE::Q2, VE::Q3, VE::Q4, VE::Q5, VE::Q6, VE::Q7,
/openbsd-current/gnu/llvm/llvm/lib/Target/ARM/
H A DARMExpandPseudoInsts.cpp1151 if ((Reg >= ARM::Q0 && Reg <= ARM::Q7) ||
1158 if (Reg >= ARM::Q0 && Reg <= ARM::Q7) {
1407 ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7})
1501 ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7})
1669 if ((Reg >= ARM::Q0 && Reg <= ARM::Q7) ||
/openbsd-current/gnu/llvm/llvm/lib/Target/Sparc/AsmParser/
H A DSparcAsmParser.cpp176 Sparc::Q4, Sparc::Q5, Sparc::Q6, Sparc::Q7,
/openbsd-current/gnu/llvm/llvm/lib/Target/VE/AsmParser/
H A DVEAsmParser.cpp127 VE::Q0, VE::Q1, VE::Q2, VE::Q3, VE::Q4, VE::Q5, VE::Q6, VE::Q7,
/openbsd-current/gnu/llvm/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1570 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1590 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
/openbsd-current/gnu/llvm/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp2551 .Case("v7", AArch64::Q7)

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