Searched refs:PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE_MASK (Results 1 - 3 of 3) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/smuio/
H A Dsmuio_11_0_0_sh_mask.h1084 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000L macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/smu/
H A Dsmu_7_1_3_sh_mask.h5681 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000 macro
H A Dsmu_7_1_2_sh_mask.h5571 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000 macro

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