Searched refs:PCIE0_BASE__INST1_SEG5 (Results 1 - 4 of 4) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/include/
H A Dbeige_goby_ip_offset.h992 #define PCIE0_BASE__INST1_SEG5 0 macro
H A Daldebaran_ip_offset.h1162 #define PCIE0_BASE__INST1_SEG5 0 macro
H A Dvangogh_ip_offset.h1192 #define PCIE0_BASE__INST1_SEG5 0 macro
H A Darct_ip_offset.h874 #define PCIE0_BASE__INST1_SEG5 0 macro

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