Searched refs:PACKET3_SET_UCONFIG_REG_START (Results 1 - 12 of 12) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/amdgpu/
H A Dvid.h352 #define PACKET3_SET_UCONFIG_REG_START 0x0000c000 macro
H A Dnvd.h336 #define PACKET3_SET_UCONFIG_REG_START 0x0000c000 macro
H A Dsoc15d.h300 #define PACKET3_SET_UCONFIG_REG_START 0x0000c000 macro
H A Dcikd.h470 #define PACKET3_SET_UCONFIG_REG_START 0x0000c000 macro
H A Dgfx_v7_0.c2040 amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_UCONFIG_REG_START);
2305 ib.ptr[1] = mmSCRATCH_REG0 - PACKET3_SET_UCONFIG_REG_START;
H A Dgfx_v9_0.c1008 amdgpu_ring_write(ring, scratch - PACKET3_SET_UCONFIG_REG_START);
3084 (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START));
H A Dgfx_v9_4_3.c265 amdgpu_ring_write(ring, xcc_offset - PACKET3_SET_UCONFIG_REG_START);
H A Dgfx_v8_0.c851 amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_UCONFIG_REG_START);
H A Dgfx_v11_0.c342 PACKET3_SET_UCONFIG_REG_START);
H A Dgfx_v10_0.c3784 PACKET3_SET_UCONFIG_REG_START);
/openbsd-current/sys/dev/pci/drm/radeon/
H A Dcikd.h1938 #define PACKET3_SET_UCONFIG_REG_START 0x00030000 macro
H A Dcik.c3465 radeon_ring_write(ring, ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2));
3737 PACKET3_SET_UCONFIG_REG_START) >> 2));
3790 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2);

Completed in 385 milliseconds