Searched refs:PACKET3_SET_CONFIG_REG_START (Results 1 - 17 of 17) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/amdgpu/
H A Dsi_enums.h260 #define PACKET3_SET_CONFIG_REG_START 0x00002000 macro
H A Dvid.h340 #define PACKET3_SET_CONFIG_REG_START 0x00002000 macro
H A Dnvd.h319 #define PACKET3_SET_CONFIG_REG_START 0x00002000 macro
H A Dsoc15d.h288 #define PACKET3_SET_CONFIG_REG_START 0x00002000 macro
H A Dcikd.h458 #define PACKET3_SET_CONFIG_REG_START 0x00002000 macro
H A Dgfx_v6_0.c1781 amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_CONFIG_REG_START);
1811 amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START));
1888 ib.ptr[1] = mmSCRATCH_REG0 - PACKET3_SET_CONFIG_REG_START;
H A Dsid.h1846 #define PACKET3_SET_CONFIG_REG_START 0x00002000 macro
H A Dgfx_v7_0.c2246 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID - PACKET3_SET_CONFIG_REG_START);
H A Dgfx_v8_0.c6137 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID - PACKET3_SET_CONFIG_REG_START);
/openbsd-current/sys/dev/pci/drm/radeon/
H A Devergreen_cs.c2300 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
2302 if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
3421 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
3423 if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
H A Dnid.h1270 #define PACKET3_SET_CONFIG_REG_START 0x00008000 macro
H A Dsi.c3377 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
3417 PACKET3_SET_CONFIG_REG_START) >> 2));
3443 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
4621 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
4623 if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
H A Dcikd.h1926 #define PACKET3_SET_CONFIG_REG_START 0x00008000 macro
H A Dsid.h1783 #define PACKET3_SET_CONFIG_REG_START 0x00008000 macro
H A Devergreend.h1666 #define PACKET3_SET_CONFIG_REG_START 0x00008000 macro
H A Dni.c1427 PACKET3_SET_CONFIG_REG_START) >> 2));
H A Devergreen.c2945 PACKET3_SET_CONFIG_REG_START) >> 2));

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