/openbsd-current/sys/dev/pci/drm/amd/amdgpu/ |
H A D | gfx_v8_0.c | 850 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 891 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 1222 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1225 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 1233 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 1244 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 1250 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1253 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 1543 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); 1549 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_RE [all...] |
H A D | gfx_v7_0.c | 2039 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 2082 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 2095 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 2099 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 2123 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 2135 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 2166 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); 2205 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2210 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 2212 header = PACKET3(PACKET3_INDIRECT_BUFFE [all...] |
H A D | si_enums.h | 168 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro 171 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
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H A D | gfx_v6_0.c | 1780 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1799 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 1810 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1813 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 1822 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 1842 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 1847 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 1849 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 1887 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); 1995 amdgpu_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZ [all...] |
H A D | gfx_v9_0.c | 771 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 793 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 823 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 851 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 870 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 963 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 977 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 1007 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 1047 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 1449 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNT [all...] |
H A D | vid.h | 105 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ macro 109 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
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H A D | nvd.h | 48 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ macro 52 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
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H A D | soc15d.h | 50 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ macro 54 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
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H A D | gfx_v11_0.c | 137 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 172 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 204 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 231 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 291 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 304 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 340 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 408 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 626 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 629 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTRO [all...] |
H A D | gfx_v9_4_3.c | 63 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 86 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 116 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 143 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 162 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 216 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 230 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 264 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 304 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 2526 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_RE [all...] |
H A D | cikd.h | 223 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ macro 227 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
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H A D | gfx_v10_0.c | 3498 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 3530 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 3562 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 3589 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 3736 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3749 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3782 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 3845 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 4083 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4086 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTRO [all...] |
H A D | amdgpu_amdkfd_gfx_v10_3.c | 302 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
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H A D | gfx_v9_4_2.c | 381 ib->ptr[ib->length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); 389 ib->ptr[ib->length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); 396 ib->ptr[ib->length_dw++] = PACKET3(PACKET3_SET_SH_REG, 3); 404 ib->ptr[ib->length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
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H A D | amdgpu_amdkfd_gfx_v10.c | 316 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
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/openbsd-current/sys/dev/pci/drm/radeon/ |
H A D | ni.c | 1398 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 1404 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 1420 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0)); 1425 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1431 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 1441 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 1547 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); 1565 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1571 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1575 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STAT [all...] |
H A D | si.c | 3376 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 3379 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 3388 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 3407 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 3410 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 3415 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 3421 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3428 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 3442 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 3445 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYN [all...] |
H A D | cik.c | 3464 radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 3520 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3549 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 3561 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 3588 radeon_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); 3619 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); 3625 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 3680 radeon_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); 3727 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 3730 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONS [all...] |
H A D | r600.c | 2697 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); 2842 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2880 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 2886 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 2894 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 2899 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 2902 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2906 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2937 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); 2944 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_M [all...] |
H A D | r300d.h | 45 /* PACKET3 op code */ 64 #define PACKET3(op, n) (CP_PACKET3 | \ macro
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H A D | cikd.h | 1691 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ macro 1695 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
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H A D | sid.h | 1595 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro 1599 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
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H A D | evergreen.c | 2938 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0)); 2943 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2949 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3)); 2956 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 3010 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); 3029 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3035 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3039 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
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H A D | rv515d.h | 188 /* PACKET3 op code */ 204 #define PACKET3(op, n) (CP_PACKET3 | \ macro
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H A D | rv770d.h | 988 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro
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