Searched refs:OperandIdx (Results 1 - 16 of 16) sorted by relevance

/openbsd-current/gnu/llvm/llvm/include/llvm/MC/
H A DMCInstrItineraries.h167 int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const {
173 if ((FirstIdx + OperandIdx) >= LastIdx)
176 return (int)OperandCycles[FirstIdx + OperandIdx];
/openbsd-current/gnu/llvm/llvm/lib/DebugInfo/DWARF/
H A DDWARFDebugFrame.cpp418 uint32_t OperandIdx) const {
419 if (OperandIdx >= MaxOperands)
422 OperandIdx);
423 OperandType Type = CFIP.getOperandTypes()[Opcode][OperandIdx];
424 uint64_t Operand = Ops[OperandIdx];
431 OperandIdx, CFIProgram::operandTypeString(Type));
440 OperandIdx);
454 OperandIdx);
463 uint32_t OperandIdx) const {
464 if (OperandIdx >
859 printOperand(raw_ostream &OS, DIDumpOptions DumpOpts, const Instruction &Instr, unsigned OperandIdx, uint64_t Operand) const argument
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/openbsd-current/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DR600Packetizer.cpp81 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::write); local
82 if (OperandIdx > -1 && BI->getOperand(OperandIdx).getImm() == 0)
131 int OperandIdx = TII->getOperandIdx(MI.getOpcode(), Op); local
132 if (OperandIdx < 0)
134 Register Src = MI.getOperand(OperandIdx).getReg();
137 MI.getOperand(OperandIdx).setReg(It->second);
H A DGCNVOPDUtils.cpp69 auto getVRegIdx = [&](unsigned OpcodeIdx, unsigned OperandIdx) {
71 const MachineOperand &Operand = MI.getOperand(OperandIdx);
H A DR600ISelLowering.cpp2094 int OperandIdx[] = { local
2125 if (OperandIdx[i] < 0)
2127 SDValue &Src = Ops[OperandIdx[i] - 1];
2131 int SelIdx = TII->getSelIdx(Opcode, OperandIdx[i]);
2147 int OperandIdx[] = { local
2163 if (OperandIdx[i] < 0)
2165 SDValue &Src = Ops[OperandIdx[i] - 1];
2170 int SelIdx = TII->getSelIdx(Opcode, OperandIdx[i]);
/openbsd-current/gnu/llvm/llvm/lib/Transforms/Utils/
H A DCanonicalizeFreezeInLoops.cpp185 unsigned OperandIdx = local
187 InsertFreezeAndForgetFromSCEV(PHI->getOperandUse(OperandIdx));
H A DScalarEvolutionExpander.cpp2272 WorkItem.ParentOpcode, WorkItem.OperandIdx, Imm, Ty, CostKind);
/openbsd-current/gnu/llvm/llvm/include/llvm/DebugInfo/DWARF/
H A DDWARFDebugFrame.h424 uint32_t OperandIdx) const;
427 uint32_t OperandIdx) const;
524 /// Print \p Opcode's operand number \p OperandIdx which has value \p Operand.
526 const Instruction &Instr, unsigned OperandIdx,
/openbsd-current/gnu/llvm/llvm/include/llvm/Transforms/Utils/
H A DScalarEvolutionExpander.h35 ParentOpcode(Opc), OperandIdx(Idx), S(S) { }
39 int OperandIdx; member in struct:llvm::SCEVOperand
/openbsd-current/gnu/llvm/llvm/lib/CodeGen/
H A DMachineFunction.cpp1178 unsigned OperandIdx = 0; local
1182 ++OperandIdx;
1184 assert(OperandIdx < DefMI.getNumOperands());
1188 MO.ChangeToDbgInstrRef(ID, OperandIdx);
H A DCodeGenPrepare.cpp7455 /// Check if promoting to a vector type an operand at \p OperandIdx
7458 unsigned OperandIdx) {
7461 if (OperandIdx != 1)
7457 canCauseUndefinedBehavior(const Instruction *Use, unsigned OperandIdx) argument
/openbsd-current/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp869 unsigned OperandIdx = 0;
873 ++OperandIdx;
875 assert(OperandIdx < DefMI->getNumOperands());
879 MOs.push_back(MachineOperand::CreateDbgInstrRef(InstrNum, OperandIdx));
/openbsd-current/gnu/llvm/llvm/lib/Transforms/Scalar/
H A DRewriteStatepointsForGC.cpp1273 auto UpdateOperand = [&](int OperandIdx) {
1274 Value *InVal = BdvIE->getOperand(OperandIdx);
1276 BaseIE->setOperand(OperandIdx, Base);
1283 auto UpdateOperand = [&](int OperandIdx) {
1284 Value *InVal = BdvSV->getOperand(OperandIdx);
1286 BaseSV->setOperand(OperandIdx, Base);
/openbsd-current/gnu/llvm/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp3559 auto getVRegIdx = [&](unsigned, unsigned OperandIdx) {
3560 const MCOperand &Opr = Inst.getOperand(OperandIdx);
6454 unsigned OperandIdx[4]; local
6464 OperandIdx[SrcIdx] = Inst.size();
6472 OperandIdx[SrcIdx] = Inst.size();
6495 Inst.getOperand(OperandIdx[1]) = Inst.getOperand(OperandIdx[2]);
6496 Inst.getOperand(OperandIdx[2]).setReg(AMDGPU::NoRegister);
6497 Inst.getOperand(OperandIdx[3]).setReg(AMDGPU::NoRegister);
6501 if (Inst.getOperand(OperandIdx[
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/openbsd-current/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.cpp1338 unsigned OperandIdx = Commuted ? 2 : 1; local
1340 *MRI.getVRegDef(Inst.getOperand(OperandIdx).getReg());
H A DRISCVISelLowering.cpp9198 /// Build a NodeExtensionHelper for \p Root.getOperand(\p OperandIdx).
9199 NodeExtensionHelper(SDNode *Root, unsigned OperandIdx, SelectionDAG &DAG) { argument
9202 assert(OperandIdx < 2 && "Requesting something else than LHS or RHS");
9203 OrigOperand = Root->getOperand(OperandIdx);
9213 if (OperandIdx == 1) {

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