Searched refs:Op1Reg (Results 1 - 10 of 10) sorted by relevance
/openbsd-current/gnu/llvm/llvm/lib/Target/X86/ |
H A D | X86CmovConversion.cpp | 828 Register Op1Reg = MIIt->getOperand(1).getReg(); local 835 std::swap(Op1Reg, Op2Reg); 837 auto Op1Itr = RegRewriteTable.find(Op1Reg); 839 Op1Reg = Op1Itr->second.first; 849 .addReg(Op1Reg) 858 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg);
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H A D | X86InstructionSelector.cpp | 1080 const Register Op1Reg = I.getOperand(3).getReg(); local 1118 .addReg(Op1Reg); 1522 const Register Op1Reg = I.getOperand(1).getReg(); local 1526 assert(RegTy == MRI.getType(Op1Reg) && RegTy == MRI.getType(Op2Reg) && 1628 if (!RBI.constrainGenericRegister(Op1Reg, *RegRC, MRI) || 1639 .addReg(Op1Reg);
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H A D | X86FastISel.cpp | 1429 Register Op1Reg = getRegForValue(Op1); 1430 if (Op1Reg == 0) return false; 1433 .addReg(Op1Reg); 1841 Register Op1Reg = getRegForValue(I->getOperand(1)); 1842 if (Op1Reg == 0) return false; 1844 CReg).addReg(Op1Reg); 1950 Register Op1Reg = getRegForValue(I->getOperand(1)); 1951 if (Op1Reg == 0) 1987 TII.get(OpEntry.OpDivRem)).addReg(Op1Reg);
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H A D | X86ISelLowering.cpp | [all...] |
/openbsd-current/gnu/llvm/llvm/lib/Target/AArch64/ |
H A D | AArch64FastISel.cpp | 256 unsigned emitLSL_rr(MVT RetVT, unsigned Op0Reg, unsigned Op1Reg); 259 unsigned emitLSR_rr(MVT RetVT, unsigned Op0Reg, unsigned Op1Reg); 262 unsigned emitASR_rr(MVT RetVT, unsigned Op0Reg, unsigned Op1Reg); 4032 unsigned Op1Reg) { 4047 Op1Reg = emitAnd_ri(MVT::i32, Op1Reg, Mask); 4049 Register ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op1Reg); 4134 unsigned Op1Reg) { 4150 Op1Reg = emitAnd_ri(MVT::i32, Op1Reg, Mas 4031 emitLSL_rr(MVT RetVT, unsigned Op0Reg, unsigned Op1Reg) argument 4133 emitLSR_rr(MVT RetVT, unsigned Op0Reg, unsigned Op1Reg) argument 4249 emitASR_rr(MVT RetVT, unsigned Op0Reg, unsigned Op1Reg) argument [all...] |
/openbsd-current/gnu/llvm/llvm/lib/Target/ARM/ |
H A D | ARMFastISel.cpp | 1612 Register Op1Reg = getRegForValue(I->getOperand(1)); 1613 if (Op1Reg == 0) return false; 1658 Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 2); 1662 .addReg(Op1Reg) 1666 Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 1); 1669 .addReg(Op1Reg)
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/openbsd-current/gnu/llvm/llvm/lib/Target/M68k/ |
H A D | M68kISelLowering.cpp | 3142 Register Op1Reg = MIIt->getOperand(1).getReg(); local 3149 std::swap(Op1Reg, Op2Reg); 3151 if (RegRewriteTable.find(Op1Reg) != RegRewriteTable.end()) 3152 Op1Reg = RegRewriteTable[Op1Reg].first; 3159 .addReg(Op1Reg) 3165 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg);
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/openbsd-current/gnu/llvm/llvm/lib/Target/Mips/ |
H A D | MipsFastISel.cpp | 2005 Register Op1Reg = getRegForValue(I->getOperand(1)); local 2006 if (!Op1Reg) 2023 emitInst(Opcode, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
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/openbsd-current/gnu/llvm/llvm/lib/Target/RISCV/ |
H A D | RISCVInstrInfo.cpp | 2174 Register Op1Reg = MI.getOperand(CommutableOpIdx1).getReg(); local 2179 if (Op1Reg != MI.getOperand(2).getReg())
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/openbsd-current/gnu/llvm/llvm/lib/CodeGen/GlobalISel/ |
H A D | LegalizerHelper.cpp | 7477 Register Op1Reg = MI.getOperand(2).getReg(); 7488 Op1Reg = MIRBuilder.buildPtrToInt(NewTy, Op1Reg).getReg(0); 7518 auto NewOp1 = MIRBuilder.buildAnd(MaskTy, Op1Reg, MaskReg);
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