Searched refs:NUM_WM_RANGES (Results 1 - 25 of 29) sorted by relevance

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/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_smu13_driver_if.h31 #define NUM_WM_RANGES 4 macro
42 WatermarkRowGeneric_t WatermarkRow[NUM_WM_RANGES];
H A Dsmu13_driver_if.h64 #define NUM_WM_RANGES 4 macro
75 WatermarkRowGeneric_t WatermarkRow[NUM_WM_RANGES];
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddcn30_smu11_driver_if.h36 #define NUM_WM_RANGES 4 macro
53 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
/openbsd-current/sys/dev/pci/drm/amd/pm/powerplay/inc/
H A Dsmu10_driver_if.h61 #define NUM_WM_RANGES 4 macro
70 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
H A Dsmu9_driver_if.h339 #define NUM_WM_RANGES 4 macro
349 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
H A Dsmu11_driver_if.h690 #define NUM_WM_RANGES 4 macro
700 WatermarkRowGeneric_t WatermarkRow[WM_COUNT_PP][NUM_WM_RANGES];
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/
H A Ddcn301_smu.h67 #define NUM_WM_RANGES 4 macro
77 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
131 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/
H A Ddcn315_smu.h51 #define NUM_WM_RANGES 4 macro
90 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
/openbsd-current/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu13_driver_if_v13_0_5.h61 #define NUM_WM_RANGES 4 macro
73 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
H A Dsmu12_driver_if.h61 #define NUM_WM_RANGES 4 macro
73 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
H A Dsmu13_driver_if_v13_0_4.h61 #define NUM_WM_RANGES 4 macro
73 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
H A Dsmu11_driver_if_vangogh.h60 #define NUM_WM_RANGES 4 macro
72 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
H A Dsmu13_driver_if_yellow_carp.h60 #define NUM_WM_RANGES 4 macro
72 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
H A Dsmu11_driver_if_navi10.h1034 #define NUM_WM_RANGES 4 macro
1044 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
H A Dsmu13_driver_if_v13_0_0.h1502 #define NUM_WM_RANGES 4 macro
1513 WatermarkRowGeneric_t WatermarkRow[NUM_WM_RANGES];
H A Dsmu13_driver_if_v13_0_7.h1492 #define NUM_WM_RANGES 4 macro
1503 WatermarkRowGeneric_t WatermarkRow[NUM_WM_RANGES];
H A Dsmu11_driver_if_sienna_cichlid.h1632 #define NUM_WM_RANGES 4 macro
1649 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_smu.h62 #define NUM_WM_RANGES 4 macro
74 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
231 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/
H A Ddcn316_smu.h50 #define NUM_WM_RANGES 4 macro
98 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_smu.h72 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
/openbsd-current/sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/
H A Dsmu9_driver_if.h583 #define NUM_WM_RANGES 4 macro
593 WatermarkRowGeneric_t WatermarkRow[WM_COUNT_PP][NUM_WM_RANGES];
/openbsd-current/sys/dev/pci/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_5_ppt.c411 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
412 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
H A Dsmu_v13_0_4_ppt.c667 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
668 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
H A Dyellow_carp_ppt.c502 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
503 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
/openbsd-current/sys/dev/pci/drm/amd/pm/swsmu/smu12/
H A Drenoir_ppt.c1051 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1052 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)

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