Searched refs:MPLL_SS1 (Results 1 - 14 of 14) sorted by relevance

/openbsd-current/sys/dev/pci/drm/radeon/
H A Drv740d.h110 #define MPLL_SS1 0x85c macro
H A Drv740_dpm.c313 pi->clk_regs.rv770.mpll_ss1 = RREG32(MPLL_SS1);
H A Dnid.h687 #define MPLL_SS1 0x85c macro
H A Dcikd.h753 #define MPLL_SS1 0x2bcc macro
H A Dsid.h630 #define MPLL_SS1 0x2bcc macro
H A Devergreend.h225 #define MPLL_SS1 0x85c macro
H A Dni_dpm.c1195 ni_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
H A Dci_dpm.c1856 pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
H A Dsi_dpm.c3565 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
/openbsd-current/sys/dev/pci/drm/amd/amdgpu/
H A Dsid.h631 #define MPLL_SS1 0xAF3 macro
/openbsd-current/sys/dev/pci/drm/amd/pm/powerplay/smumgr/
H A Diceland_smumgr.c1140 mpll_ss1 = PHM_SET_FIELD(mpll_ss1, MPLL_SS1, CLKV, clkv);
H A Dci_smumgr.c1092 mpll_ss1 = PHM_SET_FIELD(mpll_ss1, MPLL_SS1, CLKV, clkv);
H A Dtonga_smumgr.c892 mpll_ss1 = PHM_SET_FIELD(mpll_ss1, MPLL_SS1, CLKV, clkv);
/openbsd-current/sys/dev/pci/drm/amd/pm/legacy-dpm/
H A Damdgpu_si_dpm.c4039 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);

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