Searched refs:MC_SEQ_WR_CTL_D1 (Results 1 - 12 of 12) sorted by relevance

/openbsd-current/sys/dev/pci/drm/radeon/
H A Dbtcd.h112 #define MC_SEQ_WR_CTL_D1 0x28c0 macro
H A Dnid.h788 #define MC_SEQ_WR_CTL_D1 0x28c0 macro
H A Dcikd.h662 #define MC_SEQ_WR_CTL_D1 0x28c0 macro
H A Dsid.h549 #define MC_SEQ_WR_CTL_D1 0x28c0 macro
H A Dbtc_dpm.c1879 case MC_SEQ_WR_CTL_D1 >> 2:
2035 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
H A Dci_dpm.c4412 case MC_SEQ_WR_CTL_D1 >> 2:
4530 case MC_SEQ_WR_CTL_D1:
4611 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
H A Devergreend.h294 #define MC_SEQ_WR_CTL_D1 0x28c0 macro
H A Dcypress_dpm.c1003 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_WR_CTL_D1 >> 2;
H A Dni_dpm.c2797 case MC_SEQ_WR_CTL_D1 >> 2:
2894 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
H A Dsi_dpm.c5432 case MC_SEQ_WR_CTL_D1 >> 2:
5533 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
/openbsd-current/sys/dev/pci/drm/amd/amdgpu/
H A Dsid.h550 #define MC_SEQ_WR_CTL_D1 0xA30 macro
/openbsd-current/sys/dev/pci/drm/amd/pm/legacy-dpm/
H A Damdgpu_si_dpm.c5925 case MC_SEQ_WR_CTL_D1:
6026 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));

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