/openbsd-current/gnu/llvm/compiler-rt/lib/xray/ |
H A D | xray_utils.cpp | 126 LogWriter *LW = reinterpret_cast<LogWriter *>(InternalAlloc(sizeof(LogWriter))); variable 127 new (LW) LogWriter(Vmo); 128 return LW; 131 void LogWriter::Close(LogWriter *LW) { argument 132 LW->~LogWriter(); 133 InternalFree(LW); 189 LogWriter *LW = allocate<LogWriter>(); 190 new (LW) LogWriter(Fd); 191 return LW; 194 void LogWriter::Close(LogWriter *LW) { [all...] |
H A D | xray_basic_logging.cpp | 88 LogWriter* LW = LogWriter::Open(); variable 89 if (LW == nullptr) 90 return LW; 112 LW->WriteAll(reinterpret_cast<char *>(&Header), 114 return LW; 119 static LogWriter *LW = nullptr; variable 120 pthread_once(&OnceInit, +[] { LW = getLog(); }); 121 return LW; 161 LogWriter *LW = getGlobalLog(); variable 162 if (LW 261 LogWriter *LW = getGlobalLog(); variable [all...] |
H A D | xray_profiling.cpp | 244 LogWriter *LW = LogWriter::Open(); variable 245 if (LW == nullptr) { 252 LW->WriteAll(reinterpret_cast<const char *>(B.Data), 257 LogWriter::Close(LW);
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H A D | xray_fdr_logging.cpp | 340 LogWriter *LW = LogWriter::Open(); variable 341 if (LW == nullptr) { 349 LW->WriteAll(reinterpret_cast<char *>(&Header), 373 LW->WriteAll(reinterpret_cast<char *>(&ExtentsRecord), 376 LW->WriteAll(reinterpret_cast<char *>(B.Data),
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/openbsd-current/gnu/llvm/clang/utils/ABITest/ |
H A D | Enumeration.py | 152 LW,RW = W//2, W - (W//2) 153 L,R = getNthPairBounded(N, H**LW, H**RW) 154 return (getNthNTuple(L,LW,H=H,useLeftToRight=useLeftToRight) +
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/openbsd-current/gnu/llvm/llvm/lib/Target/RISCV/ |
H A D | RISCVMakeCompressible.cpp | 104 case RISCV::LW: 150 return Opcode == RISCV::LW || (!STI.is64Bit() && Opcode == RISCV::FLW) ||
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H A D | RISCVExpandPseudoInsts.cpp | 366 unsigned SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW; 377 unsigned SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW;
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H A D | RISCVSExtWRemoval.cpp | 308 return RISCV::LW;
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H A D | RISCVMergeBaseOffset.cpp | 368 case RISCV::LW:
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H A D | RISCVFrameLowering.cpp | 121 BuildMI(MBB, MI, DL, TII->get(IsRV64 ? RISCV::LD : RISCV::LW))
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H A D | RISCVInstrInfo.cpp | 79 case RISCV::LW: 564 RISCV::LW : RISCV::LD; 650 LoadOpc = RISCV::LW;
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/openbsd-current/gnu/llvm/llvm/lib/Target/Mips/ |
H A D | MipsInstructionSelector.cpp | 211 return Mips::LW; 390 MachineInstr *LW = local 391 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW)) 397 if (!constrainSelectedInstRegOperands(*LW, TII, TRI, RBI)) 402 LW->getOperand(0).setReg(DestTmp); 669 MachineInstr *LWGOT = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW)) 725 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW))
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H A D | MicroMipsSizeReduction.cpp | 157 // Attempts to reduce LW/SW instruction into LWSP/SWSP, 161 // Attempts to reduce two LW/SW instructions into LWP/SWP instruction, 240 {RT_TwoInstr, OpCodes(Mips::LW, Mips::LWP_MM), ReduceXWtoXWP, 242 {RT_OneInstr, OpCodes(Mips::LW, Mips::LWSP_MM), ReduceXWtoXWSP, 355 !(MI->getOpcode() == Mips::LW || MI->getOpcode() == Mips::LW_MM || 468 bool ReduceToLwp = (MI1->getOpcode() == Mips::LW) ||
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H A D | MipsSEInstrInfo.cpp | 49 if ((Opc == Mips::LW) || (Opc == Mips::LD) || 333 Opc = Mips::LW; 362 Opc = Mips::LW; 366 Opc = Mips::LW;
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H A D | MipsFastISel.cpp | 417 emitInst(Mips::LW, DestReg) 434 emitInst(Mips::LW, DestReg) 760 Opc = Mips::LW;
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H A D | MipsInstrInfo.cpp | 657 case Mips::LW:
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H A D | MipsBranchExpansion.cpp | 519 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA)
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/openbsd-current/gnu/llvm/lldb/source/Plugins/Instruction/RISCV/ |
H A D | RISCVInstructions.h | 115 I_TYPE_INST(LW); 276 LUI, AUIPC, JAL, JALR, B, LB, LH, LW, LBU, LHU, SB, SH, SW, ADDI, SLTI,
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H A D | RISCVCInstructions.h | 59 return LW{rd, Rs{gpr_sp_riscv}, uint32_t(offset)}; 88 return LW{DecodeCL_RD(inst), DecodeCL_RS1(inst), uint32_t(offset)};
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H A D | EmulateInstructionRISCV.cpp | 189 std::is_same_v<T, LB> || std::is_same_v<T, LH> || std::is_same_v<T, LW> || 431 {"LW", 0x707F, 0x2003, DecodeIType<LW>}, 711 bool operator()(LW inst) { 712 return Load<LW, uint32_t, int32_t>(m_emu, inst, SextW);
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/openbsd-current/gnu/llvm/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsNaClELFStreamer.cpp | 224 case Mips::LW:
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H A D | MipsTargetStreamer.cpp | 310 emitLoadWithImmOffset(Mips::LW, GPReg, Mips::SP, Offset, GPReg, IDLoc, STI); 1223 // and adds a corresponding LW after every JAL.
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/openbsd-current/gnu/llvm/lld/ELF/Arch/ |
H A D | RISCV.cpp | 58 LW = 0x2003, enumerator in enum:Op 219 uint32_t load = config->is64 ? LD : LW; 238 write32le(buf + 4, itype(config->is64 ? LD : LW, X_T3, X_T3, lo12(offset)));
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/openbsd-current/gnu/llvm/llvm/lib/Target/RISCV/AsmParser/ |
H A D | RISCVAsmParser.cpp | 2412 SecondOpcode = isRV64() ? RISCV::LD : RISCV::LW; 2431 unsigned SecondOpcode = isRV64() ? RISCV::LD : RISCV::LW; 2708 emitLoadStoreSymbol(Inst, RISCV::LW, IDLoc, Out, /*HasTmpReg=*/false);
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/openbsd-current/gnu/llvm/llvm/lib/Target/Mips/AsmParser/ |
H A D | MipsAsmParser.cpp | 2365 // We need a NOP between the JALR and the LW: 2961 TOut.emitRRX(IsPtr64 ? Mips::LD : Mips::LW, DstReg, DstReg, 2966 TOut.emitRRX(IsPtr64 ? Mips::LD : Mips::LW, DstReg, GPReg, 3006 TOut.emitRRX(IsPtr64 ? Mips::LD : Mips::LW, TmpReg, TmpReg, 3073 TOut.emitRRX(IsPtr64 ? Mips::LD : Mips::LW, TmpReg, GPReg, 3306 TOut.emitRRX(Mips::LW, ATReg, GPReg, MCOperand::createExpr(GotExpr), 3529 TOut.emitRRI(Mips::LW, FirstReg, TmpReg, 0, IDLoc, STI); 3530 TOut.emitRRI(Mips::LW, nextReg(FirstReg), TmpReg, 4, IDLoc, STI); 5325 unsigned Opcode = IsLoad ? Mips::LW : Mips::SW;
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