Searched refs:LMul (Results 1 - 6 of 6) sorted by relevance

/openbsd-current/gnu/llvm/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVBaseInfo.cpp169 unsigned LMul; local
171 std::tie(LMul, Fractional) = decodeVLMUL(getVLMUL(VType));
177 OS << LMul; local
191 unsigned LMul; local
193 std::tie(LMul, Fractional) = decodeVLMUL(VLMul);
195 // Convert LMul to a fixed point value with 3 fractional bits.
196 LMul = Fractional ? (8 / LMul) : (LMul * 8);
199 return (SEW * 8) / LMul;
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/openbsd-current/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.cpp129 RISCVII::VLMUL LMul) {
163 if (FirstLMul != LMul)
195 return LMul == RISCVVType::getVLMUL(VType);
282 RISCVII::VLMUL LMul = RISCVII::LMUL_1; local
305 LMul = RISCVII::LMUL_1;
308 LMul = RISCVII::LMUL_2;
311 LMul = RISCVII::LMUL_4;
314 LMul = RISCVII::LMUL_8;
319 LMul = RISCVII::LMUL_1;
324 LMul
125 isConvertibleToVMV_V_V(const RISCVSubtarget &STI, const MachineBasicBlock &MBB, MachineBasicBlock::const_iterator MBBI, MachineBasicBlock::const_iterator &DefMBBI, RISCVII::VLMUL LMul) argument
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H A DRISCVInsertVSETVLI.cpp1142 unsigned LMul; local
1144 std::tie(LMul, Fractional) = RISCVVType::decodeVLMUL(Info.getVLMUL());
1147 return ST.getRealMinVLen() / LMul >= AVLInBits;
1148 return ST.getRealMinVLen() * LMul >= AVLInBits;
H A DRISCVTargetTransformInfo.cpp42 unsigned LMul; local
44 std::tie(LMul, Fractional) =
49 Cost = LMul;
H A DRISCVISelLowering.h591 static unsigned getRegClassIDForLMUL(RISCVII::VLMUL LMul);
H A DRISCVISelLowering.cpp1617 unsigned RISCVTargetLowering::getRegClassIDForLMUL(RISCVII::VLMUL LMul) { argument
1618 switch (LMul) {
1799 unsigned LMul = divideCeil(VT.getSizeInBits(), MinVLen); local
1801 if (LMul > Subtarget.getMaxLMULForFixedLengthVectors())

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