Searched refs:L0 (Results 1 - 25 of 37) sorted by relevance

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/openbsd-current/gnu/llvm/compiler-rt/lib/sanitizer_common/
H A Dsanitizer_common_interceptors_vfork_i386.inc.S17 call .L0$pb
18 .L0$pb:
21 add $_GLOBAL_OFFSET_TABLE_+(.Ltmp0-.L0$pb), %eax
/openbsd-current/gnu/llvm/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp185 MachineInstr &L0 = *SU->getInstr(); local
186 if (!L0.mayLoad() || L0.mayStore() || L0.getNumMemOperands() != 1)
189 auto MO0 = *L0.memoperands().begin();
239 if (!getBaseOffset(L0, SP, SPOffset0) || SP->getReg().id() != ARM::SP)
/openbsd-current/lib/libc/arch/sh/gen/
H A D_setjmp.S120 bf .L0
122 .L0:
H A Dsetjmp.S159 bf .L0
161 .L0:
H A Dsigsetjmp.S158 bf .L0
160 .L0:
/openbsd-current/gnu/usr.bin/gcc/gcc/config/rs6000/
H A Ddarwin-tramp.asm110 bcl 20,31,L0$_abort
111 L0$_abort:
113 addis r11,r11,ha16(L_abort$lazy_ptr-L0$_abort)
115 lwz r12,lo16(L_abort$lazy_ptr-L0$_abort)(r11)
117 addi r11,r11,lo16(L_abort$lazy_ptr-L0$_abort)
/openbsd-current/gnu/gcc/gcc/config/rs6000/
H A Ddarwin-tramp.asm115 bcl 20,31,L0$_abort
116 L0$_abort:
118 addis r11,r11,ha16(L_abort$lazy_ptr-L0$_abort)
120 lgu r12,lo16(L_abort$lazy_ptr-L0$_abort)(r11)
/openbsd-current/lib/libcrypto/whrlpool/
H A Dwhirlpool.c494 u64 L0,L1,L2,L3,L4,L5,L6,L7;
526 L0 = C0(K,0) ^ C1(K,7) ^ C2(K,6) ^ C3(K,5) ^
543 K.q[0] = L0; K.q[1] = L1; K.q[2] = L2; K.q[3] = L3;
546 L0 ^= C0(S,0) ^ C1(S,7) ^ C2(S,6) ^ C3(S,5) ^
563 S.q[0] = L0; S.q[1] = L1; S.q[2] = L2; S.q[3] = L3;
566 L0 = C0(K,0); L1 = C1(K,0); L2 = C2(K,0); L3 = C3(K,0);
568 L0 ^= RC[r];
571 L5 ^= C4(K,1); L6 ^= C5(K,1); L7 ^= C6(K,1); L0 ^= C7(K,1);
574 L6 ^= C4(K,2); L7 ^= C5(K,2); L0 ^= C6(K,2); L1 ^= C7(K,2);
577 L7 ^= C4(K,3); L0
[all...]
/openbsd-current/gnu/usr.bin/gcc/gcc/config/mn10200/
H A Dlib1funcs.asm55 bge .L0
59 .L0:
209 beq .L0
215 .L0:
228 beq .L0
234 .L0:
247 beq .L0
253 .L0:
/openbsd-current/gnu/llvm/compiler-rt/lib/xray/
H A Dxray_allocator.h245 SpinMutexLock L0(&Mutex);
260 SpinMutexLock L0(&Mutex);
/openbsd-current/libexec/getty/
H A Dgettytab.h111 #define L0 gettynums[16].value macro
H A Dsubr.c179 tmode.c_lflag = L0;
/openbsd-current/gnu/llvm/llvm/lib/Transforms/Vectorize/
H A DLoadStoreVectorizer.cpp1167 LoadInst *L0 = cast<LoadInst>(Chain[0]); local
1185 unsigned AS = L0->getPointerAddressSpace();
1189 Align Alignment = L0->getAlign();
1245 if (L0->getPointerAddressSpace() != DL.getAllocaAddrSpace()) {
1258 Align NewAlign = getOrEnforceKnownAlignment(L0->getPointerOperand(),
1260 DL, L0, nullptr, &DT);
1289 Builder.CreateBitCast(L0->getPointerOperand(), VecTy->getPointerTo(AS));
1324 reorder((BCInst && BCInst != L0->getPointerOperand()) ? BCInst : LI);
/openbsd-current/gnu/usr.bin/gcc/gcc/config/ip2k/
H A Dip2k.c261 OUT_AS2 (mov, w, %L0);
358 OUT_AS2 (mov, w, %L0);
428 OUT_AS2 (mov, w, %L0);
471 OUT_AS2 (mov, w, %L0);
488 OUT_AS2 (mov, w, %L0);
1183 OUT_AS2 (or, w, %L0);
1224 OUT_AS2 (cmp, w, %L0);
1443 OUT_AS2 (or, w, %L0);
1496 OUT_AS2 (or, w, %L0);
1550 OUT_AS1 (push, %L0
[all...]
/openbsd-current/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp393 MachineInstr &L0 = *S0.getInstr(); local
394 if (!L0.mayLoad() || L0.mayStore() ||
395 HII.getAddrMode(L0) != HexagonII::BaseImmOffset)
399 MachineOperand *BaseOp0 = HII.getBaseAndOffset(L0, Offset0, Size0);
/openbsd-current/gnu/llvm/llvm/lib/Target/Sparc/
H A DSparcFrameLowering.cpp316 for (unsigned reg = SP::L0; reg <= SP::L7; ++reg)
330 || MRI.isPhysRegUsed(SP::L0) // Too many registers needed
/openbsd-current/gnu/gcc/gcc/config/m68hc11/
H A Dlarith.asm298 L0: label
309 bne L0
355 L0: label
359 bne L0
/openbsd-current/gnu/usr.bin/gcc/gcc/config/m68hc11/
H A Dlarith.asm298 L0: label
309 bne L0
355 L0: label
359 bne L0
/openbsd-current/gnu/usr.bin/binutils/gdb/
H A Dsparc-stub.c112 L0, L1, L2, L3, L4, L5, L6, L7, enumerator in enum:regnames
/openbsd-current/gnu/gcc/gcc/config/ia64/
H A Dlib1funcs.asm626 mov.ret.sptk rp = in0, .L0
658 .L0: { .mib
711 .L0: { .mib
/openbsd-current/gnu/usr.bin/gcc/gcc/config/ia64/
H A Dlib1funcs.asm571 mov.ret.sptk rp = in0, .L0
603 .L0: { .mib
656 .L0: { .mib
/openbsd-current/gnu/llvm/llvm/lib/Transforms/Scalar/
H A DLoopFuse.cpp1274 bool accessDiffIsPositive(const Loop &L0, const Loop &L1, Instruction &I0, argument
1281 const SCEV *SCEVPtr0 = SE.getSCEVAtScope(Ptr0, &L0);
1288 AddRecLoopReplacer Rewriter(SE, L0, L1);
1299 // L0) and the other is not. We could check if it is monotone and test
1302 BasicBlock *L0Header = L0.getHeader();
1325 /// Return true if the dependences between @p I0 (in @p L0) and @p I1 (in
1326 /// @p L1) allow loop fusion of @p L0 and @p L1. The dependence analyses
/openbsd-current/gnu/llvm/llvm/lib/Transforms/InstCombine/
H A DInstCombineAndOrXor.cpp1056 std::optional<IntPart> L0 = matchIntPart(Cmp0->getOperand(0));
1060 if (!L0 || !R0 || !L1 || !R1)
1065 if (L0->From != L1->From || R0->From != R1->From) {
1066 if (L0->From != R1->From || R0->From != L1->From)
1071 // Make sure the extracted parts are adjacent, canonicalizing to L0/R0 being
1073 if (L0->StartBit + L0->NumBits != L1->StartBit ||
1075 if (L1->StartBit + L1->NumBits != L0->StartBit ||
1078 std::swap(L0, L1);
1083 IntPart L = {L0
[all...]
/openbsd-current/gnu/llvm/llvm/lib/Target/Sparc/AsmParser/
H A DSparcAsmParser.cpp149 Sparc::L0, Sparc::L1, Sparc::L2, Sparc::L3,
480 else if (Reg >= Sparc::L0 && Reg <= Sparc::L7)
481 regIdx = Reg - Sparc::L0 + 16;
/openbsd-current/gnu/llvm/llvm/lib/Target/Sparc/Disassembler/
H A DSparcDisassembler.cpp65 SP::L0, SP::L1, SP::L2, SP::L3,

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