Searched refs:GraphicsLevel (Results 1 - 18 of 18) sorted by relevance

/openbsd-current/sys/dev/pci/drm/radeon/
H A Dsmu7_fusion.h233 SMU7_Fusion_GraphicsLevel GraphicsLevel [SMU__NUM_SCLK_DPM_STATE]; member in struct:SMU7_Fusion_DpmTable
H A Dsmu7_discrete.h322 SMU7_Discrete_GraphicsLevel GraphicsLevel [SMU7_MAX_LEVELS_GRAPHICS]; member in struct:SMU7_Discrete_DpmTable
H A Dci_dpm.c3242 offsetof(SMU7_Discrete_DpmTable, GraphicsLevel);
3245 SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel;
3254 &pi->smc_state_table.GraphicsLevel[i]);
3258 pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
3260 pi->smc_state_table.GraphicsLevel[i].DisplayWatermark =
3263 pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
H A Dkv_dpm.c613 offsetof(SMU7_Fusion_DpmTable, GraphicsLevel),
1601 offsetof(SMU7_Fusion_DpmTable, GraphicsLevel) +
/openbsd-current/sys/dev/pci/drm/amd/pm/powerplay/inc/
H A Dsmu7_fusion.h224 SMU7_Fusion_GraphicsLevel GraphicsLevel[SMU__NUM_SCLK_DPM_STATE]; member in struct:SMU7_Fusion_DpmTable
H A Dsmu71_discrete.h211 // Use this instead of copies of the GraphicsLevel and MemoryLevel structures to keep track of state parameters
270 SMU71_Discrete_GraphicsLevel GraphicsLevel [SMU71_MAX_LEVELS_GRAPHICS]; member in struct:SMU71_Discrete_DpmTable
H A Dsmu7_discrete.h323 SMU7_Discrete_GraphicsLevel GraphicsLevel [SMU7_MAX_LEVELS_GRAPHICS]; member in struct:SMU7_Discrete_DpmTable
H A Dsmu72_discrete.h265 SMU72_Discrete_GraphicsLevel GraphicsLevel[SMU72_MAX_LEVELS_GRAPHICS]; member in struct:SMU72_Discrete_DpmTable
H A Dsmu74_discrete.h282 SMU74_Discrete_GraphicsLevel GraphicsLevel[SMU74_MAX_LEVELS_GRAPHICS]; member in struct:SMU74_Discrete_DpmTable
H A Dsmu75_discrete.h287 SMU75_Discrete_GraphicsLevel GraphicsLevel [SMU75_MAX_LEVELS_GRAPHICS]; member in struct:SMU75_Discrete_DpmTable
H A Dsmu73_discrete.h239 SMU73_Discrete_GraphicsLevel GraphicsLevel[SMU73_MAX_LEVELS_GRAPHICS]; member in struct:SMU73_Discrete_DpmTable
/openbsd-current/sys/dev/pci/drm/amd/pm/powerplay/smumgr/
H A Dtonga_smumgr.c695 offsetof(SMU72_Discrete_DpmTable, GraphicsLevel);
700 SMU72_Discrete_GraphicsLevel *levels = smu_data->smc_state_table.GraphicsLevel;
713 &(smu_data->smc_state_table.GraphicsLevel[i]));
719 smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
723 smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
727 smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark =
741 smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel =
771 smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled;
774 smu_data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled;
777 smu_data->smc_state_table.GraphicsLevel[
[all...]
H A Diceland_smumgr.c965 offsetof(SMU71_Discrete_DpmTable, GraphicsLevel);
970 SMU71_Discrete_GraphicsLevel *levels = smu_data->smc_state_table.GraphicsLevel;
983 &(smu_data->smc_state_table.GraphicsLevel[i]));
989 smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
993 smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
997 smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark =
1027 smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled;
1031 smu_data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled;
1034 smu_data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled;
H A Dfiji_smumgr.c250 level_addr = table_start + offsetof(SMU73_Discrete_DpmTable, GraphicsLevel);
1011 offsetof(SMU73_Discrete_DpmTable, GraphicsLevel);
1015 smu_data->smc_state_table.GraphicsLevel;
1745 GraphicsLevel[smu_data->smc_state_table.GraphicsDpmLevelCount - 1].
1789 smu_data->smc_state_table.GraphicsLevel[j].SclkFrequency);
2556 smu_data->smc_state_table.GraphicsLevel;
2558 offsetof(SMU73_Discrete_DpmTable, GraphicsLevel);
H A Dpolaris10_smumgr.c147 graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
1047 offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
1051 smu_data->smc_state_table.GraphicsLevel;
1071 &(smu_data->smc_state_table.GraphicsLevel[i]));
1081 smu_data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;
1103 smu_data->smc_state_table.GraphicsLevel[i].EnabledForActivity =
2594 smu_data->smc_state_table.GraphicsLevel;
2596 offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
H A Dci_smumgr.c479 offsetof(SMU7_Discrete_DpmTable, GraphicsLevel);
483 smu_data->smc_state_table.GraphicsLevel;
493 smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
495 smu_data->smc_state_table.GraphicsLevel[i].DisplayWatermark =
499 smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
2767 smu_data->smc_state_table.GraphicsLevel;
2769 offsetof(SMU7_Discrete_DpmTable, GraphicsLevel);
H A Dvegam_smumgr.c875 offsetof(SMU75_Discrete_DpmTable, GraphicsLevel);
879 smu_data->smc_state_table.GraphicsLevel;
892 &(smu_data->smc_state_table.GraphicsLevel[i]));
906 smu_data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;
/openbsd-current/sys/dev/pci/drm/amd/pm/legacy-dpm/
H A Damdgpu_kv_dpm.c844 offsetof(SMU7_Fusion_DpmTable, GraphicsLevel),
1838 offsetof(SMU7_Fusion_DpmTable, GraphicsLevel) +

Completed in 402 milliseconds