Searched refs:GRBM_SOFT_RESET (Results 1 - 20 of 20) sorted by relevance

/openbsd-current/sys/dev/pci/drm/radeon/
H A Dni.c1652 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1658 RREG32(GRBM_SOFT_RESET);
1660 WREG32(GRBM_SOFT_RESET, 0);
1661 RREG32(GRBM_SOFT_RESET);
1907 tmp = RREG32(GRBM_SOFT_RESET);
1909 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
1910 WREG32(GRBM_SOFT_RESET, tmp);
1911 tmp = RREG32(GRBM_SOFT_RESET);
1916 WREG32(GRBM_SOFT_RESET, tmp);
1917 tmp = RREG32(GRBM_SOFT_RESET);
[all...]
H A Devergreen.c3073 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
3079 RREG32(GRBM_SOFT_RESET);
3081 WREG32(GRBM_SOFT_RESET, 0);
3082 RREG32(GRBM_SOFT_RESET);
3975 tmp = RREG32(GRBM_SOFT_RESET);
3977 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
3978 WREG32(GRBM_SOFT_RESET, tmp);
3979 tmp = RREG32(GRBM_SOFT_RESET);
3984 WREG32(GRBM_SOFT_RESET, tmp);
3985 tmp = RREG32(GRBM_SOFT_RESET);
[all...]
H A Drv770.c1105 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1106 RREG32(GRBM_SOFT_RESET);
1108 WREG32(GRBM_SOFT_RESET, 0);
H A Dr600.c2661 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2662 RREG32(GRBM_SOFT_RESET);
2664 WREG32(GRBM_SOFT_RESET, 0);
2724 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2725 RREG32(GRBM_SOFT_RESET);
2727 WREG32(GRBM_SOFT_RESET, 0);
H A Dsi.c3950 tmp = RREG32(GRBM_SOFT_RESET);
3952 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
3953 WREG32(GRBM_SOFT_RESET, tmp);
3954 tmp = RREG32(GRBM_SOFT_RESET);
3959 WREG32(GRBM_SOFT_RESET, tmp);
3960 tmp = RREG32(GRBM_SOFT_RESET);
5808 u32 tmp = RREG32(GRBM_SOFT_RESET);
5811 WREG32(GRBM_SOFT_RESET, tmp);
5814 WREG32(GRBM_SOFT_RESET, tmp);
H A Drv770d.h401 #define GRBM_SOFT_RESET 0x8020 macro
H A Dnid.h280 #define GRBM_SOFT_RESET 0x8020 macro
H A Dcikd.h1075 #define GRBM_SOFT_RESET 0x8020 macro
H A Dsid.h982 #define GRBM_SOFT_RESET 0x8020 macro
H A Dcik.c5009 tmp = RREG32(GRBM_SOFT_RESET);
5011 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
5012 WREG32(GRBM_SOFT_RESET, tmp);
5013 tmp = RREG32(GRBM_SOFT_RESET);
5018 WREG32(GRBM_SOFT_RESET, tmp);
5019 tmp = RREG32(GRBM_SOFT_RESET);
H A Devergreend.h828 #define GRBM_SOFT_RESET 0x8020 macro
H A Dr600d.h295 #define GRBM_SOFT_RESET 0x8020 macro
/openbsd-current/sys/dev/pci/drm/amd/amdgpu/
H A Dgfx_v8_0.c4061 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
4064 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
4944 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
4946 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
4955 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
4960 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4962 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4964 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
5004 if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
5005 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GF
[all...]
H A Dgfx_v11_0.c1788 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
1790 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
4498 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4500 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4502 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4504 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4506 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4511 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4513 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4515 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
[all...]
H A Dgfx_v9_4_3.c1193 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET,
1196 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET,
2099 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
2101 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
2106 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
2113 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2126 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
H A Dgfx_v9_0.c2842 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2844 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
3871 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3873 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
3878 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3885 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
3902 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
H A Dsdma_v5_2.c706 GRBM_SOFT_RESET, SOFT_RESET_SDMA0,
712 DRM_DEBUG("GRBM_SOFT_RESET=0x%08X\n", tmp);
H A Dgfx_v6_0.c2460 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2462 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
H A Dgfx_v10_0.c5061 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
5063 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
7238 GRBM_SOFT_RESET, SOFT_RESET_CP,
7241 GRBM_SOFT_RESET, SOFT_RESET_GFX,
7247 GRBM_SOFT_RESET, SOFT_RESET_CP,
7263 GRBM_SOFT_RESET,
7270 GRBM_SOFT_RESET,
7289 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
H A Dsid.h980 #define GRBM_SOFT_RESET 0x2008 macro

Completed in 793 milliseconds