| /openbsd-current/sys/dev/pci/drm/amd/amdgpu/ |
| H A D | gfxhub_v3_0_3.c | 197 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
387 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
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| H A D | gfxhub_v2_0.c | 193 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
374 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
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| H A D | gfxhub_v1_0.c | 161 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
358 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
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| H A D | gfxhub_v3_0.c | 192 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
394 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
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| H A D | mmhub_v2_0.c | 262 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
455 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
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| H A D | mmhub_v2_3.c | 192 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
387 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
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| H A D | mmhub_v3_0.c | 218 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
412 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
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| H A D | mmhub_v3_0_1.c | 217 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
399 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
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| H A D | mmhub_v3_0_2.c | 210 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
404 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
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| H A D | gfxhub_v2_1.c | 194 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
395 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
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| H A D | mmhub_v1_8.c | 200 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB,
446 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB,
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| H A D | mmhub_v1_0.c | 144 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
354 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
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| H A D | gfxhub_v1_2.c | 205 ENABLE_L1_TLB, 1);
447 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
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| H A D | mmhub_v1_7.c | 162 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
362 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
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| H A D | gmc_v7_0.c | 620 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
740 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
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| H A D | mmhub_v9_4.c | 185 ENABLE_L1_TLB, 1);
424 ENABLE_L1_TLB, 0);
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| H A D | gmc_v8_0.c | 835 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
972 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
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| /openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn30/ |
| H A D | dcn30_hubp.c | 64 ENABLE_L1_TLB, 1,
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| /openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn10/ |
| H A D | dcn10_hubp.h | 409 HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, mask_sh),\
610 type ENABLE_L1_TLB;\
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| H A D | dcn10_hubp.c | 821 ENABLE_L1_TLB, 1,
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| /openbsd-current/sys/dev/pci/drm/radeon/ |
| H A D | rv770d.h | 465 #define ENABLE_L1_TLB (1 << 0) macro
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| H A D | rv770.c | 913 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
990 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
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| H A D | nid.h | 179 #define ENABLE_L1_TLB (1 << 0) macro
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| H A D | cikd.h | 600 #define ENABLE_L1_TLB (1 << 0) macro
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| /openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn21/ |
| H A D | dcn21_hubp.c | 247 ENABLE_L1_TLB, 1,
|