Searched refs:DispClocks (Results 1 - 13 of 13) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_smu.h51 uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS]; member in struct:__anon261
H A Ddcn314_clk_mgr.c591 max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled);
653 bw_params->clk_table.entries[i].dispclk_mhz = find_max_clk_value(clock_table->DispClocks, NUM_DISPCLK_DPM_LEVELS);
810 DC_LOG_SMU("smu_dpm_clks.dpm_clks->DispClocks[%d] = %d\n",
811 i, smu_dpm_clks.dpm_clks->DispClocks[i]);
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/
H A Ddcn315_smu.h71 uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS]; member in struct:__anon265
H A Ddcn315_clk_mgr.c516 bw_params->clk_table.entries[i].dispclk_mhz = clock_table->DispClocks[i];
532 bw_params->clk_table.entries[i-1].dispclk_mhz = clock_table->DispClocks[clock_table->NumDispClkLevelsEnabled - 1];
695 DC_LOG_SMU("smu_dpm_clks.dpm_clks->DispClocks[%d] = %d\n",
696 i, smu_dpm_clks.dpm_clks->DispClocks[i]);
/openbsd-current/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu13_driver_if_v13_0_5.h112 uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS]; member in struct:__anon627
H A Dsmu13_driver_if_v13_0_4.h124 uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS]; member in struct:__anon618
H A Dsmu11_driver_if_vangogh.h129 uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS]; member in struct:__anon506
H A Dsmu13_driver_if_yellow_carp.h123 uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS]; member in struct:__anon722
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/
H A Ddcn301_smu.h100 uint32_t DispClocks[VG_NUM_DISPCLK_DPM_LEVELS]; member in struct:vg_dpm_clocks
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/
H A Ddcn316_smu.h79 uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS]; member in struct:__anon270
H A Ddcn316_clk_mgr.c510 max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled);
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_smu.h132 uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS]; member in struct:__anon257
H A Ddcn31_clk_mgr.c587 max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled);
768 DC_LOG_SMU("smu_dpm_clks.dpm_clks->DispClocks[%d] = %d\n",
769 i, smu_dpm_clks.dpm_clks->DispClocks[i]);

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