Searched refs:DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT (Results 1 - 3 of 3) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_4_2_0_sh_mask.h75007 #define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT macro
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H A Ddpcs_4_2_2_sh_mask.h75205 #define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT macro
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H A Ddpcs_4_2_3_sh_mask.h71571 #define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT macro
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