Searched refs:DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT (Results 1 - 4 of 4) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_3_1_4_sh_mask.h9446 #define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 macro
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H A Ddpcs_4_2_0_sh_mask.h16199 #define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT macro
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H A Ddpcs_4_2_2_sh_mask.h16331 #define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT macro
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H A Ddpcs_4_2_3_sh_mask.h15772 #define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT macro
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