| /openbsd-current/gnu/usr.bin/binutils/opcodes/ |
| H A D | m10200-opc.c | 28 #define DN0 (UNUSED+1)
32 #define DN1 (DN0+1)
169 { "mov", 0xf3f0, 0xfffc, FMT_4, {PSW, DN0}},
171 { "mov", 0xf3e0, 0xfffc, FMT_4, {MDR, DN0}},
178 { "mov", 0xc80000, 0xfc0000, FMT_3, {MEM(IMM16_MEM), DN0}},
179 { "mov", 0xf4c00000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), DN0}},
192 { "mov", 0xc00000, 0xfc0000, FMT_3, {DN0, MEM(IMM16_MEM)}},
193 { "mov", 0xf4400000, 0xfffc0000, FMT_7, {DN0, MEM(IMM24_MEM)}},
201 { "mov", 0xf80000, 0xfc0000, FMT_3, {SIMM16, DN0}},
202 { "mov", 0xf4700000, 0xfffc0000, FMT_7, {IMM24, DN0}},
27 #define DN0 macro
[all...] |
| H A D | m10300-opc.c | 30 #define DN0 (UNUSED+1)
34 #define DN1 (DN0+1)
448 { "mov", 0x80, 0xf0, 0x3, FMT_S0, 0, {DM1, DN0}},
450 { "mov", 0xf1d0, 0xfff0, 0, FMT_D0, 0, {AM1, DN0}},
455 { "mov", 0xf2e4, 0xfffc, 0, FMT_D0, 0, {PSW, DN0}},
457 { "mov", 0xf2e0, 0xfffc, 0, FMT_D0, 0, {MDR, DN0}},
460 { "mov", 0x5800, 0xfcff, 0, FMT_S1, 0, {MEM(SP), DN0}},
461 { "mov", 0x300000, 0xfc0000, 0, FMT_S2, 0, {MEM(IMM16_MEM), DN0}},
474 { "mov", 0x5800, 0xfc00, 0, FMT_S1, 0, {MEM2(IMM8, SP), DN0}},
475 { "mov", 0xfab40000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), DN0}},
29 #define DN0 macro
[all...] |
| /openbsd-current/gnu/usr.bin/binutils-2.17/opcodes/ |
| H A D | m10200-opc.c | 28 #define DN0 (UNUSED+1)
32 #define DN1 (DN0+1)
169 { "mov", 0xf3f0, 0xfffc, FMT_4, {PSW, DN0}},
171 { "mov", 0xf3e0, 0xfffc, FMT_4, {MDR, DN0}},
178 { "mov", 0xc80000, 0xfc0000, FMT_3, {MEM(IMM16_MEM), DN0}},
179 { "mov", 0xf4c00000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), DN0}},
192 { "mov", 0xc00000, 0xfc0000, FMT_3, {DN0, MEM(IMM16_MEM)}},
193 { "mov", 0xf4400000, 0xfffc0000, FMT_7, {DN0, MEM(IMM24_MEM)}},
201 { "mov", 0xf80000, 0xfc0000, FMT_3, {SIMM16, DN0}},
202 { "mov", 0xf4700000, 0xfffc0000, FMT_7, {IMM24, DN0}},
27 #define DN0 macro
[all...] |
| H A D | m10300-opc.c | 31 #define DN0 (UNUSED+1)
35 #define DN1 (DN0+1)
449 { "mov", 0x80, 0xf0, 0x3, FMT_S0, 0, {DM1, DN0}},
451 { "mov", 0xf1d0, 0xfff0, 0, FMT_D0, 0, {AM1, DN0}},
456 { "mov", 0xf2e4, 0xfffc, 0, FMT_D0, 0, {PSW, DN0}},
458 { "mov", 0xf2e0, 0xfffc, 0, FMT_D0, 0, {MDR, DN0}},
461 { "mov", 0x5800, 0xfcff, 0, FMT_S1, 0, {MEM(SP), DN0}},
462 { "mov", 0x300000, 0xfc0000, 0, FMT_S2, 0, {MEM(IMM16_MEM), DN0}},
475 { "mov", 0x5800, 0xfc00, 0, FMT_S1, 0, {MEM2(IMM8, SP), DN0}},
476 { "mov", 0xfab40000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), DN0}},
30 #define DN0 macro
[all...] |