Searched refs:DMA_CNTL (Results 1 - 11 of 11) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/amdgpu/
H A Damdgpu_si_dma.c169 dma_cntl = RREG32(DMA_CNTL + sdma_offsets[i]);
171 WREG32(DMA_CNTL + sdma_offsets[i], dma_cntl);
596 sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET);
598 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl);
601 sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET);
603 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl);
612 sdma_cntl = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET);
614 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, sdma_cntl);
617 sdma_cntl = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET);
619 WREG32(DMA_CNTL
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H A Dsid.h1897 #define DMA_CNTL 0x340b macro
/openbsd-current/sys/dev/pci/drm/radeon/
H A Dni_dma.c238 dma_cntl = RREG32(DMA_CNTL + reg_offset);
240 WREG32(DMA_CNTL + reg_offset, dma_cntl);
H A Dr600_dma.c159 dma_cntl = RREG32(DMA_CNTL);
161 WREG32(DMA_CNTL, dma_cntl);
H A Dsi.c5957 tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
5958 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, tmp);
5959 tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
5960 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp);
6073 dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
6074 dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
6106 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, dma_cntl);
6107 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, dma_cntl1);
H A Dnid.h1323 #define DMA_CNTL 0xd02c macro
H A Dr600.c3623 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
3624 WREG32(DMA_CNTL, tmp);
3805 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
3874 WREG32(DMA_CNTL, dma_cntl);
H A Dsid.h1833 #define DMA_CNTL 0xd02c macro
H A Devergreen.c4474 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
4475 WREG32(DMA_CNTL, tmp);
4521 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
4570 WREG32(DMA_CNTL, dma_cntl);
H A Devergreend.h1404 #define DMA_CNTL 0xd02c macro
H A Dr600d.h631 #define DMA_CNTL 0xd02c macro

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