Searched refs:DC_HPD1_INT_CONTROL (Results 1 - 11 of 11) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/display/dc/irq/dce60/
H A Dirq_service_dce60.c68 DC_HPD1_INT_CONTROL,
/openbsd-current/sys/dev/pci/drm/amd/display/dc/irq/dce80/
H A Dirq_service_dce80.c59 DC_HPD1_INT_CONTROL,
/openbsd-current/sys/dev/pci/drm/radeon/
H A Dr600.c868 tmp = RREG32(DC_HPD1_INT_CONTROL);
873 WREG32(DC_HPD1_INT_CONTROL, tmp);
3632 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3633 WREG32(DC_HPD1_INT_CONTROL, tmp);
3784 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3880 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3951 tmp = RREG32(DC_HPD1_INT_CONTROL);
3953 WREG32(DC_HPD1_INT_CONTROL, tmp);
H A Dcik.c6909 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
6910 WREG32(DC_HPD1_INT_CONTROL, tmp);
7041 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
7263 WREG32(DC_HPD1_INT_CONTROL, hpd1);
7364 tmp = RREG32(DC_HPD1_INT_CONTROL);
7366 WREG32(DC_HPD1_INT_CONTROL, tmp);
7394 tmp = RREG32(DC_HPD1_INT_CONTROL);
7396 WREG32(DC_HPD1_INT_CONTROL, tmp);
H A Dcikd.h954 #define DC_HPD1_INT_CONTROL 0x6020 macro
H A Dsid.h880 #define DC_HPD1_INT_CONTROL 0x6020 macro
H A Devergreend.h1346 #define DC_HPD1_INT_CONTROL 0x6020 macro
H A Dr600d.h856 #define DC_HPD1_INT_CONTROL 0x7d04 macro
H A Devergreen.c50 #define DC_HPDx_INT_CONTROL(x) (DC_HPD1_INT_CONTROL + (x * 0xc))
H A Dsi.c162 #define DC_HPDx_INT_CONTROL(x) (DC_HPD1_INT_CONTROL + (x * 0xc))
/openbsd-current/sys/dev/pci/drm/amd/amdgpu/
H A Dsid.h883 #define DC_HPD1_INT_CONTROL 0x1808 macro

Completed in 466 milliseconds