Searched refs:DCN_BASE__INST0_SEG0 (Results 1 - 16 of 16) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/display/dmub/src/
H A Ddmub_dcn315.c33 #define DCN_BASE__INST0_SEG0 0x00000012 macro
H A Ddmub_dcn316.c33 #define DCN_BASE__INST0_SEG0 0x00000012 macro
H A Ddmub_dcn314.c33 #define DCN_BASE__INST0_SEG0 0x00000012 macro
/openbsd-current/sys/dev/pci/drm/amd/display/dc/gpio/dcn315/
H A Dhw_factory_dcn315.c45 #define DCN_BASE__INST0_SEG0 0x00000012 macro
H A Dhw_translate_dcn315.c38 #define DCN_BASE__INST0_SEG0 0x00000012 macro
/openbsd-current/sys/dev/pci/drm/amd/display/dc/irq/dcn315/
H A Dirq_service_dcn315.c38 #define DCN_BASE__INST0_SEG0 0x00000012 macro
/openbsd-current/sys/dev/pci/drm/amd/include/
H A Dnavi10_ip_offset.h267 #define DCN_BASE__INST0_SEG0 0x00000012 macro
H A Dbeige_goby_ip_offset.h441 #define DCN_BASE__INST0_SEG0 0x00000012 macro
H A Ddimgrey_cavefish_ip_offset.h363 #define DCN_BASE__INST0_SEG0 0x00000012 macro
H A Drenoir_ip_offset.h1369 #define DCN_BASE__INST0_SEG0 0x00000012 macro
H A Dvega10_ip_offset.h305 #define DCN_BASE__INST0_SEG0 0x00000012 macro
H A Dsienna_cichlid_ip_offset.h370 #define DCN_BASE__INST0_SEG0 0x00000012 macro
H A Dyellow_carp_offset.h385 #define DCN_BASE__INST0_SEG0 0x00000012 macro
H A Dvangogh_ip_offset.h452 #define DCN_BASE__INST0_SEG0 0x00000012 macro
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn315/
H A Ddcn315_resource.c96 #define DCN_BASE__INST0_SEG0 0x00000012 macro
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn316/
H A Ddcn316_resource.c94 #define DCN_BASE__INST0_SEG0 0x00000012 macro

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