Searched refs:DCN_1_0__SRCID__DC_D3_OTG_V_UPDATE (Results 1 - 1 of 1) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/include/ivsrcid/dcn/
H A Dirqsrcs_dcn_1_0.h566 #define DCN_1_0__SRCID__DC_D3_OTG_V_UPDATE 0x1A // D3 : OTG V_update OTG3_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse macro

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