Searched refs:CondCodes (Results 1 - 25 of 40) sorted by relevance

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/openbsd-current/gnu/llvm/llvm/lib/Target/MSP430/
H A DMSP430.h22 enum CondCodes { enum in namespace:MSP430CC
H A DMSP430InstrInfo.cpp136 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm());
219 MSP430CC::CondCodes BranchCode =
220 static_cast<MSP430CC::CondCodes>(I->getOperand(1).getImm());
242 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm();
/openbsd-current/gnu/llvm/llvm/lib/Target/AVR/
H A DAVRInstrInfo.h31 enum CondCodes { enum in namespace:llvm::AVRCC
69 const MCInstrDesc &getBrCond(AVRCC::CondCodes CC) const;
70 AVRCC::CondCodes getCondFromBranchOpc(unsigned Opc) const;
71 AVRCC::CondCodes getOppositeCondition(AVRCC::CondCodes CC) const;
H A DAVRInstrInfo.cpp190 const MCInstrDesc &AVRInstrInfo::getBrCond(AVRCC::CondCodes CC) const {
213 AVRCC::CondCodes AVRInstrInfo::getCondFromBranchOpc(unsigned Opc) const {
236 AVRCC::CondCodes AVRInstrInfo::getOppositeCondition(AVRCC::CondCodes CC) const {
318 AVRCC::CondCodes BranchCode = getCondFromBranchOpc(I->getOpcode());
380 AVRCC::CondCodes OldBranchCode = (AVRCC::CondCodes)Cond[0].getImm();
415 AVRCC::CondCodes CC = (AVRCC::CondCodes)Cond[0].getImm();
468 AVRCC::CondCodes C
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/openbsd-current/gnu/llvm/llvm/lib/Target/ARM/Utils/
H A DARMBaseInfo.h28 // The CondCodes constants map directly to the 4-bit encoding of the
30 enum CondCodes { // Meaning (integer) Meaning (floating-point) enum in namespace:llvm::ARMCC
48 inline static CondCodes getOppositeCondition(CondCodes CC) {
71 inline static ARMCC::CondCodes getSwappedCondition(ARMCC::CondCodes CC) {
146 inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
/openbsd-current/gnu/llvm/llvm/lib/Target/ARM/
H A DThumb2ITBlockPass.cpp67 ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
137 ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
187 ARMCC::CondCodes NCC = getITInstrPredicate(*I, NPredReg);
203 ARMCC::CondCodes CC = getITInstrPredicate(*MI, PredReg);
226 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
244 ARMCC::CondCodes NCC = getITInstrPredicate(*NMI, NPredReg);
H A DThumbRegisterInfo.h42 int Val, ARMCC::CondCodes Pred = ARMCC::AL,
H A DThumb2InstrInfo.h78 ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, Register &PredReg);
H A DARMBaseInstrInfo.h165 ARMCC::CondCodes getPredicate(const MachineInstr &MI) const {
167 return PIdx != -1 ? (ARMCC::CondCodes)MI.getOperand(PIdx).getImm()
542 static inline std::array<MachineOperand, 2> predOps(ARMCC::CondCodes Pred,
783 ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, Register &PredReg);
799 ARMCC::CondCodes Pred, Register PredReg,
806 ARMCC::CondCodes Pred, Register PredReg,
H A DARMLoadStoreOptimizer.cpp175 ARMCC::CondCodes Pred, unsigned PredReg);
179 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
185 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
489 ARMCC::CondCodes Pred,
630 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
837 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
908 ARMCC::CondCodes Pred = getInstrPredicate(*First, PredReg);
1191 ARMCC::CondCodes Pred, Register PredReg) {
1223 ARMCC::CondCodes Pred, Register PredReg, int &Offset) {
1243 ARMCC::CondCodes Pre
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H A DThumbRegisterInfo.cpp65 ARMCC::CondCodes Pred, unsigned PredReg,
85 ARMCC::CondCodes Pred, unsigned PredReg,
106 ARMCC::CondCodes Pred, Register PredReg, unsigned MIFlags) const {
H A DARMInstructionSelector.cpp54 ARMCC::CondCodes Cond, unsigned LHSReg, unsigned RHSReg,
391 static std::pair<ARMCC::CondCodes, ARMCC::CondCodes>
393 std::pair<ARMCC::CondCodes, ARMCC::CondCodes> Preds = {ARMCC::AL, ARMCC::AL};
575 ARMCC::CondCodes Cond,
H A DMLxExpansionPass.cpp281 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NextOp).getImm();
H A DARMBlockPlacement.cpp280 MIB.addImm(ARMCC::CondCodes::AL);
H A DARMBaseRegisterInfo.h216 int Val, ARMCC::CondCodes Pred = ARMCC::AL,
H A DThumb2SizeReduction.cpp187 bool is2Addr, ARMCC::CondCodes Pred,
331 bool is2Addr, ARMCC::CondCodes Pred,
801 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);
893 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);
H A DARMBaseRegisterInfo.cpp499 ARMCC::CondCodes Pred, Register PredReg, unsigned MIFlags) const {
850 ARMCC::CondCodes Pred = (PIdx == -1)
851 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
H A DMVETPAndVPTOptimisationsPass.cpp574 static ARMCC::CondCodes GetCondCode(MachineInstr &Instr) {
576 return ARMCC::CondCodes(Instr.getOperand(3).getImm());
593 ARMCC::CondCodes ExpectedCode = GetCondCode(Cond);
H A DThumb2InstrInfo.cpp74 ARMCC::CondCodes CC = getInstrPredicate(*Tail, PredReg);
295 ARMCC::CondCodes Pred, Register PredReg,
768 ARMCC::CondCodes llvm::getITInstrPredicate(const MachineInstr &MI,
/openbsd-current/gnu/llvm/llvm/lib/Target/Sparc/
H A DSparc.h41 enum CondCodes { enum in namespace:llvm::SPCC
105 inline static const char *SPARCCondCodeToString(SPCC::CondCodes CC) {
H A DSparcInstrInfo.cpp80 static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC)
371 SPCC::CondCodes CC = static_cast<SPCC::CondCodes>(Cond[1].getImm());
/openbsd-current/gnu/llvm/llvm/lib/Target/NVPTX/
H A DNVPTX.h28 enum CondCodes { enum in namespace:llvm::NVPTXCC
/openbsd-current/gnu/llvm/llvm/lib/Target/Sparc/MCTargetDesc/
H A DSparcInstPrinter.cpp209 O << SPARCCondCodeToString((SPCC::CondCodes)CC);
/openbsd-current/gnu/llvm/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.cpp961 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
972 if ((ARMCC::CondCodes)MI->getOperand(OpNum).getImm() == ARMCC::HS)
982 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
990 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
/openbsd-current/gnu/llvm/llvm/tools/llvm-exegesis/lib/X86/
H A DTarget.cpp967 auto CondCodes = enum_seq_inclusive(X86::CondCode::COND_O, local
970 Choices.reserve(CondCodes.size());
971 for (int CondCode : CondCodes)

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