Searched refs:CP_INT_CNTL_RING0 (Results 1 - 10 of 10) sorted by relevance
/openbsd-current/sys/dev/pci/drm/amd/amdgpu/ |
H A D | gfx_v11_0.c | 1753 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1755 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1757 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1759 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 5741 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5743 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5749 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5751 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5910 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0, 5929 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0, [all...] |
H A D | gfx_v9_0.c | 2474 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 2475 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 2476 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 2478 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0); 5717 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5787 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5806 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5832 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5841 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
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H A D | gfx_v9_4_3.c | 1167 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 1168 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 1169 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 2769 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 2792 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0,
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H A D | gfx_v8_0.c | 3858 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 3859 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 3860 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 3861 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0); 6413 WREG32_FIELD(CP_INT_CNTL_RING0, TIME_STAMP_INT_ENABLE, 6473 WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_REG_INT_ENABLE, 6484 WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_INSTR_INT_ENABLE, 6550 WREG32_FIELD(CP_INT_CNTL_RING0, CP_ECC_ERROR_INT_ENABLE, enable_flag);
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H A D | gfx_v10_0.c | 5018 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 5020 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 5022 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 5024 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 8788 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 8794 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 8961 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 8980 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
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H A D | sid.h | 1304 #define CP_INT_CNTL_RING0 0x306A macro
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/openbsd-current/sys/dev/pci/drm/radeon/ |
H A D | si.c | 5147 u32 tmp = RREG32(CP_INT_CNTL_RING0); 5155 WREG32(CP_INT_CNTL_RING0, tmp); 5952 tmp = RREG32(CP_INT_CNTL_RING0) & 5954 WREG32(CP_INT_CNTL_RING0, tmp); 6070 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) & 6102 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
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H A D | cik.c | 5760 u32 tmp = RREG32(CP_INT_CNTL_RING0); 5766 WREG32(CP_INT_CNTL_RING0, tmp); 6859 tmp = RREG32(CP_INT_CNTL_RING0) & 6861 WREG32(CP_INT_CNTL_RING0, tmp); 7037 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) & 7217 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
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H A D | cikd.h | 1331 #define CP_INT_CNTL_RING0 0xC1A8 macro
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H A D | sid.h | 1276 #define CP_INT_CNTL_RING0 0xC1A8 macro
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