Searched refs:CLK_BASE__INST4_SEG2 (Results 1 - 14 of 14) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/include/
H A Dcyan_skillfish_ip_offset.h199 #define CLK_BASE__INST4_SEG2 0 macro
H A Dnavi10_ip_offset.h213 #define CLK_BASE__INST4_SEG2 0 macro
H A Dvega20_ip_offset.h240 #define CLK_BASE__INST4_SEG2 0 macro
H A Dbeige_goby_ip_offset.h275 #define CLK_BASE__INST4_SEG2 0 macro
H A Ddimgrey_cavefish_ip_offset.h246 #define CLK_BASE__INST4_SEG2 0 macro
H A Drenoir_ip_offset.h345 #define CLK_BASE__INST4_SEG2 0 macro
H A Dnavi12_ip_offset.h263 #define CLK_BASE__INST4_SEG2 0 macro
H A Dnavi14_ip_offset.h263 #define CLK_BASE__INST4_SEG2 0 macro
H A Dvega10_ip_offset.h1231 #define CLK_BASE__INST4_SEG2 0 macro
H A Dsienna_cichlid_ip_offset.h270 #define CLK_BASE__INST4_SEG2 0 macro
H A Dyellow_carp_offset.h317 #define CLK_BASE__INST4_SEG2 0 macro
H A Daldebaran_ip_offset.h347 #define CLK_BASE__INST4_SEG2 0 macro
H A Dvangogh_ip_offset.h370 #define CLK_BASE__INST4_SEG2 0 macro
H A Darct_ip_offset.h332 #define CLK_BASE__INST4_SEG2 0x0042D800 macro

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