Searched refs:CLK_BASE__INST1_SEG2 (Results 1 - 14 of 14) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/include/
H A Dcyan_skillfish_ip_offset.h181 #define CLK_BASE__INST1_SEG2 0 macro
H A Dnavi10_ip_offset.h192 #define CLK_BASE__INST1_SEG2 0 macro
H A Dvega20_ip_offset.h219 #define CLK_BASE__INST1_SEG2 0 macro
H A Dbeige_goby_ip_offset.h254 #define CLK_BASE__INST1_SEG2 0 macro
H A Ddimgrey_cavefish_ip_offset.h225 #define CLK_BASE__INST1_SEG2 0 macro
H A Drenoir_ip_offset.h327 #define CLK_BASE__INST1_SEG2 0 macro
H A Dnavi12_ip_offset.h245 #define CLK_BASE__INST1_SEG2 0 macro
H A Dnavi14_ip_offset.h245 #define CLK_BASE__INST1_SEG2 0 macro
H A Dvega10_ip_offset.h1213 #define CLK_BASE__INST1_SEG2 0 macro
H A Dsienna_cichlid_ip_offset.h252 #define CLK_BASE__INST1_SEG2 0 macro
H A Dyellow_carp_offset.h296 #define CLK_BASE__INST1_SEG2 0 macro
H A Daldebaran_ip_offset.h326 #define CLK_BASE__INST1_SEG2 0 macro
H A Dvangogh_ip_offset.h349 #define CLK_BASE__INST1_SEG2 0 macro
H A Darct_ip_offset.h311 #define CLK_BASE__INST1_SEG2 0x00401C00 macro

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